plug-in tileable rr generator which can be enable by a XML property
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cf82d87e11
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548242b368
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@ -928,6 +928,7 @@ typedef struct s_direct_inf {
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/* Detailed routing architecture */
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typedef struct s_arch t_arch;
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struct s_arch {
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bool tileable; /* Xifan TANG: tileable rr_graph support */
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t_chan_width_dist Chans;
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enum e_switch_block_type SBType;
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float R_minW_nmos;
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@ -2062,6 +2062,25 @@ static void ProcessLayout(INOUTP ezxml_t Node, OUTP struct s_arch *arch) {
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arch->clb_grid.Aspect);
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}
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}
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/* Xifan TANG: Tileable Routing Support
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* Load tileable_routing if applicable
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*/
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arch->tileable = false;
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Prop = FindProperty(Node, "tileable_routing", FALSE);
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if (Prop != NULL) {
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if ( 0 == strcmp("on", Prop)) {
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arch->tileable = true;
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}
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ezxml_set_attr(Node, "tileable_routing", NULL);
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}
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if (true == arch->tileable) {
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vpr_printf(TIO_MESSAGE_INFO,
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"Tileable routing architecture generation is enabled.\n");
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} else {
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vpr_printf(TIO_MESSAGE_INFO,
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"Tileable routing architecture generation is disable. FPGA may not be tileable! \n");
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}
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}
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/* Takes in node pointing to <device> and loads all the
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@ -542,6 +542,7 @@ static void SetupRoutingArch(INP t_arch Arch,
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RoutingArch->directionality = BI_DIRECTIONAL;
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if (Arch.Segments)
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RoutingArch->directionality = Arch.Segments[0].directionality;
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RoutingArch->tileable = Arch.tileable;
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}
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static void SetupRouterOpts(INP t_options Options, INP boolean TimingEnabled,
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@ -296,10 +296,15 @@ static int binary_search_place_and_route(struct s_placer_opts placer_opts,
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if (router_opts.route_type == GLOBAL) {
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graph_type = GRAPH_GLOBAL;
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} else {
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graph_type = (
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det_routing_arch.directionality == BI_DIRECTIONAL ?
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GRAPH_BIDIR : GRAPH_UNIDIR);
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/* Xifan Tang: tileable undirectional rr_graph support */
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} else if (BI_DIRECTIONAL == det_routing_arch.directionality) {
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graph_type = GRAPH_BIDIR;
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} else if (UNI_DIRECTIONAL == det_routing_arch.directionality) {
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if (true == det_routing_arch.tileable) {
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graph_type = GRAPH_UNIDIR_TILEABLE;
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} else {
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graph_type = GRAPH_UNIDIR;
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}
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}
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max_pins_per_clb = 0;
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@ -815,6 +815,7 @@ struct s_det_routing_arch {
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float R_minW_pmos;
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int num_swseg_pattern; /*Xifan TANG: Switch Segment Pattern Support*/
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short opin_to_wire_switch; /* mrFPGA: Xifan TANG*/
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bool tileable; /* Xifan Tang: tileable rr_graph support */
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};
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/* Defines the detailed routing architecture of the FPGA. Only important *
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@ -1103,7 +1103,7 @@ void build_rr_graph_direct_connections(t_rr_graph* rr_graph,
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***********************************************************************/
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void build_tileable_unidir_rr_graph(INP const int L_num_types,
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INP t_type_ptr types, INP const int L_nx, INP const int L_ny,
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INP const struct s_grid_tile **L_grid, INP const int chan_width,
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INP struct s_grid_tile **L_grid, INP const int chan_width,
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INP const enum e_switch_block_type sb_type, INP const int Fs,
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INP const int num_seg_types,
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INP const t_segment_inf * segment_inf,
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@ -13,7 +13,7 @@ ChanNodeDetails build_unidir_chan_node_details(const size_t chan_width, const si
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void build_tileable_unidir_rr_graph(INP const int L_num_types,
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INP t_type_ptr types, INP const int L_nx, INP const int L_ny,
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INP const struct s_grid_tile **L_grid, INP const int chan_width,
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INP struct s_grid_tile **L_grid, INP const int chan_width,
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INP const enum e_switch_block_type sb_type, INP const int Fs,
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INP const int num_seg_types,
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INP const t_segment_inf * segment_inf,
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@ -273,10 +273,15 @@ boolean try_route(int width_fac, struct s_router_opts router_opts,
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if (router_opts.route_type == GLOBAL) {
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graph_type = GRAPH_GLOBAL;
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} else {
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graph_type = (
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det_routing_arch.directionality == BI_DIRECTIONAL ?
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GRAPH_BIDIR : GRAPH_UNIDIR);
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/* Xifan Tang: tileable undirectional rr_graph support */
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} else if (BI_DIRECTIONAL == det_routing_arch.directionality) {
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graph_type = GRAPH_BIDIR;
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} else if (UNI_DIRECTIONAL == det_routing_arch.directionality) {
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if (true == det_routing_arch.tileable) {
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graph_type = GRAPH_UNIDIR_TILEABLE;
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} else {
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graph_type = GRAPH_UNIDIR;
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}
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}
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/* Set the channel widths */
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@ -16,6 +16,8 @@
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#include "read_xml_arch_file.h"
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#include "ReadOptions.h"
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#include "rr_graph_tileable_builder.h"
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/* Xifan TANG: SWSEG SUPPORT */
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#include "rr_graph_swseg.h"
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/* end */
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@ -180,10 +182,31 @@ static void print_distribution(FILE * fptr,
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static t_seg_details *alloc_and_load_global_route_seg_details(
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INP int nodes_per_chan, INP int global_route_switch);
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static
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void build_classic_rr_graph(INP t_graph_type graph_type, INP int L_num_types,
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INP t_type_ptr types, INP int L_nx, INP int L_ny,
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INP struct s_grid_tile **L_grid, INP int chan_width,
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INP struct s_chan_width_dist *chan_capacity_inf,
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INP enum e_switch_block_type sb_type, INP int Fs, INP int num_seg_types,
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INP int num_switches, INP t_segment_inf * segment_inf,
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INP int global_route_switch, INP int delayless_switch,
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INP t_timing_inf timing_inf, INP int wire_to_ipin_switch,
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INP enum e_base_cost_type base_cost_type, INP t_direct_inf *directs,
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INP int num_directs, INP boolean ignore_Fc_0, OUTP int *Warnings,
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/*Xifan TANG: Switch Segment Pattern Support*/
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INP int num_swseg_pattern, INP t_swseg_pattern_inf* swseg_patterns,
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INP boolean opin_to_cb_fast_edges, INP boolean opin_logic_eq_edges);
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/* UDSD Modifications by WMF End */
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/******************* Subroutine definitions *******************************/
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/*************************************************************************
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* Top-level function of rr_graph builder
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* Xifan TANG: this top function can branch between tileable rr_graph generator
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* and the classical rr_graph generator
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************************************************************************/
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void build_rr_graph(INP t_graph_type graph_type, INP int L_num_types,
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INP t_type_ptr types, INP int L_nx, INP int L_ny,
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INP struct s_grid_tile **L_grid, INP int chan_width,
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@ -197,6 +220,50 @@ void build_rr_graph(INP t_graph_type graph_type, INP int L_num_types,
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/*Xifan TANG: Switch Segment Pattern Support*/
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INP int num_swseg_pattern, INP t_swseg_pattern_inf* swseg_patterns,
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INP boolean opin_to_cb_fast_edges, INP boolean opin_logic_eq_edges) {
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/* Branch here */
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if (GRAPH_UNIDIR_TILEABLE == graph_type) {
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build_tileable_unidir_rr_graph(L_num_types, types,
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L_nx, L_ny, L_grid,
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chan_width,
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sb_type, Fs, num_seg_types, segment_inf,
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num_switches, global_route_switch, delayless_switch,
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timing_inf, wire_to_ipin_switch,
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base_cost_type, directs, num_directs, ignore_Fc_0, Warnings);
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} else {
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build_classic_rr_graph(graph_type, L_num_types, types,
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L_nx, L_ny, L_grid,
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chan_width, chan_capacity_inf,
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sb_type, Fs, num_seg_types, num_switches, segment_inf,
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global_route_switch, delayless_switch,
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timing_inf, wire_to_ipin_switch,
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base_cost_type, directs, num_directs, ignore_Fc_0, Warnings,
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num_swseg_pattern, swseg_patterns,
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opin_to_cb_fast_edges, opin_logic_eq_edges);
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}
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return;
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}
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/* Xifan TANG: I rename the classical rr_graph builder here.
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* We can have a clean build_rr_graph top function,
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* where we branch for tileable routing and classical */
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static
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void build_classic_rr_graph(INP t_graph_type graph_type, INP int L_num_types,
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INP t_type_ptr types, INP int L_nx, INP int L_ny,
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INP struct s_grid_tile **L_grid, INP int chan_width,
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INP struct s_chan_width_dist *chan_capacity_inf,
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INP enum e_switch_block_type sb_type, INP int Fs, INP int num_seg_types,
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INP int num_switches, INP t_segment_inf * segment_inf,
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INP int global_route_switch, INP int delayless_switch,
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INP t_timing_inf timing_inf, INP int wire_to_ipin_switch,
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INP enum e_base_cost_type base_cost_type, INP t_direct_inf *directs,
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INP int num_directs, INP boolean ignore_Fc_0, OUTP int *Warnings,
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/*Xifan TANG: Switch Segment Pattern Support*/
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INP int num_swseg_pattern, INP t_swseg_pattern_inf* swseg_patterns,
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INP boolean opin_to_cb_fast_edges, INP boolean opin_logic_eq_edges) {
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/* Temp structures used to build graph */
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int nodes_per_chan, i, j;
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t_seg_details *seg_details = NULL;
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