riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

plug-in tileable rr generator which can be enable by a XML property

This commit is contained in:
tangxifan 2019-06-20 21:06:26 -06:00
parent cf82d87e11
commit 548242b368
9 changed files with 109 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
vpr7_x2p/libarchfpga/SRC/include/physical_types.h
View File

@ -928,6 +928,7 @@ typedef struct s_direct_inf {
/* Detailed routing architecture */
typedef struct s_arch t_arch;
struct s_arch {
bool tileable; /* Xifan TANG: tileable rr_graph support */
t_chan_width_dist Chans;
enum e_switch_block_type SBType;
float R_minW_nmos;

19
vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c
View File

@ -2062,6 +2062,25 @@ static void ProcessLayout(INOUTP ezxml_t Node, OUTP struct s_arch *arch) {
arch->clb_grid.Aspect);
}
}
/* Xifan TANG: Tileable Routing Support
* Load tileable_routing if applicable
*/
arch->tileable = false;
Prop = FindProperty(Node, "tileable_routing", FALSE);
if (Prop != NULL) {
if ( 0 == strcmp("on", Prop)) {
arch->tileable = true;
}
ezxml_set_attr(Node, "tileable_routing", NULL);
}
if (true == arch->tileable) {
vpr_printf(TIO_MESSAGE_INFO,
"Tileable routing architecture generation is enabled.\n");
} else {
vpr_printf(TIO_MESSAGE_INFO,
"Tileable routing architecture generation is disable. FPGA may not be tileable! \n");
}
}
/* Takes in node pointing to <device> and loads all the

1
vpr7_x2p/vpr/SRC/base/SetupVPR.c
View File

@ -542,6 +542,7 @@ static void SetupRoutingArch(INP t_arch Arch,
RoutingArch->directionality = BI_DIRECTIONAL;
if (Arch.Segments)
RoutingArch->directionality = Arch.Segments[0].directionality;
RoutingArch->tileable = Arch.tileable;
}
static void SetupRouterOpts(INP t_options Options, INP boolean TimingEnabled,

13
vpr7_x2p/vpr/SRC/base/place_and_route.c
View File

@ -296,10 +296,15 @@ static int binary_search_place_and_route(struct s_placer_opts placer_opts,
if (router_opts.route_type == GLOBAL) {
graph_type = GRAPH_GLOBAL;
} else {
graph_type = (
det_routing_arch.directionality == BI_DIRECTIONAL ?
GRAPH_BIDIR : GRAPH_UNIDIR);
/* Xifan Tang: tileable undirectional rr_graph support */
} else if (BI_DIRECTIONAL == det_routing_arch.directionality) {
graph_type = GRAPH_BIDIR;
} else if (UNI_DIRECTIONAL == det_routing_arch.directionality) {
if (true == det_routing_arch.tileable) {
graph_type = GRAPH_UNIDIR_TILEABLE;
} else {
graph_type = GRAPH_UNIDIR;
}
}
max_pins_per_clb = 0;

1
vpr7_x2p/vpr/SRC/base/vpr_types.h
View File

@ -815,6 +815,7 @@ struct s_det_routing_arch {
float R_minW_pmos;
int num_swseg_pattern; /*Xifan TANG: Switch Segment Pattern Support*/
short opin_to_wire_switch; /* mrFPGA: Xifan TANG*/
bool tileable; /* Xifan Tang: tileable rr_graph support */
};
/* Defines the detailed routing architecture of the FPGA. Only important *

2
vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_tileable_builder.c
View File

@ -1103,7 +1103,7 @@ void build_rr_graph_direct_connections(t_rr_graph* rr_graph,
***********************************************************************/
void build_tileable_unidir_rr_graph(INP const int L_num_types,
INP t_type_ptr types, INP const int L_nx, INP const int L_ny,
INP const struct s_grid_tile **L_grid, INP const int chan_width,
INP struct s_grid_tile **L_grid, INP const int chan_width,
INP const enum e_switch_block_type sb_type, INP const int Fs,
INP const int num_seg_types,
INP const t_segment_inf * segment_inf,

2
vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_tileable_builder.h
View File

@ -13,7 +13,7 @@ ChanNodeDetails build_unidir_chan_node_details(const size_t chan_width, const si
void build_tileable_unidir_rr_graph(INP const int L_num_types,
INP t_type_ptr types, INP const int L_nx, INP const int L_ny,
INP const struct s_grid_tile **L_grid, INP const int chan_width,
INP struct s_grid_tile **L_grid, INP const int chan_width,
INP const enum e_switch_block_type sb_type, INP const int Fs,
INP const int num_seg_types,
INP const t_segment_inf * segment_inf,

13
vpr7_x2p/vpr/SRC/route/route_common.c
View File

@ -273,10 +273,15 @@ boolean try_route(int width_fac, struct s_router_opts router_opts,
if (router_opts.route_type == GLOBAL) {
graph_type = GRAPH_GLOBAL;
} else {
graph_type = (
det_routing_arch.directionality == BI_DIRECTIONAL ?
GRAPH_BIDIR : GRAPH_UNIDIR);
/* Xifan Tang: tileable undirectional rr_graph support */
} else if (BI_DIRECTIONAL == det_routing_arch.directionality) {
graph_type = GRAPH_BIDIR;
} else if (UNI_DIRECTIONAL == det_routing_arch.directionality) {
if (true == det_routing_arch.tileable) {
graph_type = GRAPH_UNIDIR_TILEABLE;
} else {
graph_type = GRAPH_UNIDIR;
}
}
/* Set the channel widths */

67
vpr7_x2p/vpr/SRC/route/rr_graph.c
View File

@ -16,6 +16,8 @@
#include "read_xml_arch_file.h"
#include "ReadOptions.h"
#include "rr_graph_tileable_builder.h"
/* Xifan TANG: SWSEG SUPPORT */
#include "rr_graph_swseg.h"
/* end */
@ -180,10 +182,31 @@ static void print_distribution(FILE * fptr,
static t_seg_details *alloc_and_load_global_route_seg_details(
INP int nodes_per_chan, INP int global_route_switch);
static
void build_classic_rr_graph(INP t_graph_type graph_type, INP int L_num_types,
INP t_type_ptr types, INP int L_nx, INP int L_ny,
INP struct s_grid_tile **L_grid, INP int chan_width,
INP struct s_chan_width_dist *chan_capacity_inf,
INP enum e_switch_block_type sb_type, INP int Fs, INP int num_seg_types,
INP int num_switches, INP t_segment_inf * segment_inf,
INP int global_route_switch, INP int delayless_switch,
INP t_timing_inf timing_inf, INP int wire_to_ipin_switch,
INP enum e_base_cost_type base_cost_type, INP t_direct_inf *directs,
INP int num_directs, INP boolean ignore_Fc_0, OUTP int *Warnings,
/*Xifan TANG: Switch Segment Pattern Support*/
INP int num_swseg_pattern, INP t_swseg_pattern_inf* swseg_patterns,
INP boolean opin_to_cb_fast_edges, INP boolean opin_logic_eq_edges);
/* UDSD Modifications by WMF End */
/******************* Subroutine definitions *******************************/
/*************************************************************************
* Top-level function of rr_graph builder
* Xifan TANG: this top function can branch between tileable rr_graph generator
* and the classical rr_graph generator
************************************************************************/
void build_rr_graph(INP t_graph_type graph_type, INP int L_num_types,
INP t_type_ptr types, INP int L_nx, INP int L_ny,
INP struct s_grid_tile **L_grid, INP int chan_width,
@ -197,6 +220,50 @@ void build_rr_graph(INP t_graph_type graph_type, INP int L_num_types,
/*Xifan TANG: Switch Segment Pattern Support*/
INP int num_swseg_pattern, INP t_swseg_pattern_inf* swseg_patterns,
INP boolean opin_to_cb_fast_edges, INP boolean opin_logic_eq_edges) {
/* Branch here */
if (GRAPH_UNIDIR_TILEABLE == graph_type) {
build_tileable_unidir_rr_graph(L_num_types, types,
L_nx, L_ny, L_grid,
chan_width,
sb_type, Fs, num_seg_types, segment_inf,
num_switches, global_route_switch, delayless_switch,
timing_inf, wire_to_ipin_switch,
base_cost_type, directs, num_directs, ignore_Fc_0, Warnings);
} else {
build_classic_rr_graph(graph_type, L_num_types, types,
L_nx, L_ny, L_grid,
chan_width, chan_capacity_inf,
sb_type, Fs, num_seg_types, num_switches, segment_inf,
global_route_switch, delayless_switch,
timing_inf, wire_to_ipin_switch,
base_cost_type, directs, num_directs, ignore_Fc_0, Warnings,
num_swseg_pattern, swseg_patterns,
opin_to_cb_fast_edges, opin_logic_eq_edges);
}
return;
}
/* Xifan TANG: I rename the classical rr_graph builder here.
* We can have a clean build_rr_graph top function,
* where we branch for tileable routing and classical */
static
void build_classic_rr_graph(INP t_graph_type graph_type, INP int L_num_types,
INP t_type_ptr types, INP int L_nx, INP int L_ny,
INP struct s_grid_tile **L_grid, INP int chan_width,
INP struct s_chan_width_dist *chan_capacity_inf,
INP enum e_switch_block_type sb_type, INP int Fs, INP int num_seg_types,
INP int num_switches, INP t_segment_inf * segment_inf,
INP int global_route_switch, INP int delayless_switch,
INP t_timing_inf timing_inf, INP int wire_to_ipin_switch,
INP enum e_base_cost_type base_cost_type, INP t_direct_inf *directs,
INP int num_directs, INP boolean ignore_Fc_0, OUTP int *Warnings,
/*Xifan TANG: Switch Segment Pattern Support*/
INP int num_swseg_pattern, INP t_swseg_pattern_inf* swseg_patterns,
INP boolean opin_to_cb_fast_edges, INP boolean opin_logic_eq_edges) {
/* Temp structures used to build graph */
int nodes_per_chan, i, j;
t_seg_details *seg_details = NULL;