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Merge branch 'multimode_clb' into tileable_routing

This commit is contained in:
tangxifan 2019-06-20 18:18:20 -06:00
parent baab9c4a21 be25b6dd66
commit cf82d87e11
2 changed files with 637 additions and 51 deletions
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4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
View File

@ -1767,9 +1767,11 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
/* Definition ends*/
/* Local wires for memory configurations */
dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info,
if (0 < num_conf_bits) {
dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info,
stamped_sram_cnt,
stamped_sram_cnt + num_conf_bits - 1);
}
/* Quote all child pb_types */
for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) {

684
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c
View File

@ -1102,15 +1102,14 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
fprintf(fp, "# L%d wire, Path ID: %d\n",
L_wire,
path_cnt);
/* Report timing for the SB MUX delay, from the drive_rr_node to the wire_rr_node */
verilog_generate_one_report_timing_within_sb(fp, src_sb_info,
drive_rr_node,
src_rr_node);
if (NULL != rpt_name) {
fprintf(fp, " > %s\n", rpt_name);
} else {
fprintf(fp, "\n");
}
fprintf(fp, "report_timing -from ");
/* output instance name */
fprintf(fp, "%s/",
gen_verilog_one_sb_instance_name(src_sb_info));
/* Find which side the ending pin locates, and determine the coordinate */
dump_verilog_one_sb_routing_pin(fp, src_sb_info, drive_rr_node);
/* Switch depends on the type of des_rr_node */
switch(des_rr_node->type) {
@ -1230,18 +1229,34 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
for (ix = src_sb_info->x; ix < end_sb_x; ix++) {
/* If this is the ending point, we add a ending segment */
if (ix == end_sb_x - 1) {
verilog_generate_report_timing_one_sb_ending_segments(fp,
&(sb_info[ix][cur_sb_y]), src_rr_node,
des_rr_node,
rpt_name);
switch (des_rr_node->type) {
case IPIN:
/* Get the coordinate of ending CB */
next_cb = get_chan_rr_node_ending_cb(src_rr_node, des_rr_node);
fprintf(fp, " -to ");
fprintf(fp, "%s/",
gen_verilog_one_cb_instance_name(next_cb));
/* output pin name */
fprintf(fp, "%s",
gen_verilog_routing_channel_one_midout_name( next_cb,
src_rr_node->ptc_num));
fprintf(fp, " -point_to_point");
fprintf(fp, " -unconstrained");
break;
case CHANX:
case CHANY:
/* Get the coordinate of ending SB */
next_sb = get_chan_rr_node_ending_sb(src_rr_node, des_rr_node);
fprintf(fp, " -to ");
fprintf(fp, "%s/",
gen_verilog_one_sb_instance_name(next_sb));
/* Find which side the ending pin locates, and determine the coordinate */
dump_verilog_one_sb_chan_pin(fp, next_sb, src_rr_node, IN_PORT);
continue;
fprintf(fp, " -point_to_point");
fprintf(fp, " -unconstrained");
}
}
/* Report timing for the downstream segements, from a SB output to an adjacent CB input */
verilog_generate_report_timing_one_sb_thru_segments(fp,
&(sb_info[ix][cur_sb_y]), src_rr_node,
&(sb_info[ix + 1][cur_sb_y]), src_rr_node,
rpt_name);
}
} else if ((INC_DIRECTION == src_rr_node->direction)
&&(CHANY == src_rr_node->type)) {
@ -1249,17 +1264,34 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
for (iy = src_sb_info->y; iy < end_sb_y; iy++) {
/* If this is the ending point, we add a ending segment */
if (iy == end_sb_y - 1) {
verilog_generate_report_timing_one_sb_ending_segments(fp,
&(sb_info[cur_sb_x][iy]), src_rr_node,
des_rr_node,
rpt_name);
continue;
switch (des_rr_node->type) {
case IPIN:
/* Get the coordinate of ending CB */
next_cb = get_chan_rr_node_ending_cb(src_rr_node, des_rr_node);
fprintf(fp, " -to ");
fprintf(fp, "%s/",
gen_verilog_one_cb_instance_name(next_cb));
/* output pin name */
fprintf(fp, "%s",
gen_verilog_routing_channel_one_midout_name( next_cb,
src_rr_node->ptc_num));
fprintf(fp, " -point_to_point");
fprintf(fp, " -unconstrained");
break;
case CHANX:
case CHANY:
/* Get the coordinate of ending SB */
next_sb = get_chan_rr_node_ending_sb(src_rr_node, des_rr_node);
fprintf(fp, " -to ");
fprintf(fp, "%s/",
gen_verilog_one_sb_instance_name(next_sb));
/* Find which side the ending pin locates, and determine the coordinate */
dump_verilog_one_sb_chan_pin(fp, next_sb, src_rr_node, IN_PORT);
fprintf(fp, " -point_to_point");
fprintf(fp, " -unconstrained");
}
}
/* Report timing for the downstream segements, from a SB output to an adjacent CB input */
verilog_generate_report_timing_one_sb_thru_segments(fp,
&(sb_info[cur_sb_x][iy]), src_rr_node,
&(sb_info[cur_sb_x][iy + 1]), src_rr_node,
rpt_name);
}
} else if ((DEC_DIRECTION == src_rr_node->direction)
&&(CHANX == src_rr_node->type)) {
@ -1267,17 +1299,34 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
for (ix = src_sb_info->x - 1; ix > end_sb_x; ix--) {
/* If this is the ending point, we add a ending segment */
if (ix == end_sb_x + 1) {
verilog_generate_report_timing_one_sb_ending_segments(fp,
&(sb_info[ix][cur_sb_y]), src_rr_node,
des_rr_node,
rpt_name);
continue;
switch (des_rr_node->type) {
case IPIN:
/* Get the coordinate of ending CB */
next_cb = get_chan_rr_node_ending_cb(src_rr_node, des_rr_node);
fprintf(fp, " -to ");
fprintf(fp, "%s/",
gen_verilog_one_cb_instance_name(next_cb));
/* output pin name */
fprintf(fp, "%s",
gen_verilog_routing_channel_one_midout_name( next_cb,
src_rr_node->ptc_num));
fprintf(fp, " -point_to_point");
fprintf(fp, " -unconstrained");
break;
case CHANX:
case CHANY:
/* Get the coordinate of ending SB */
next_sb = get_chan_rr_node_ending_sb(src_rr_node, des_rr_node);
fprintf(fp, " -to ");
fprintf(fp, "%s/",
gen_verilog_one_sb_instance_name(next_sb));
/* Find which side the ending pin locates, and determine the coordinate */
dump_verilog_one_sb_chan_pin(fp, next_sb, src_rr_node, IN_PORT);
fprintf(fp, " -point_to_point");
fprintf(fp, " -unconstrained");
}
}
/* Report timing for the downstream segements, from a SB output to an adjacent CB input */
verilog_generate_report_timing_one_sb_thru_segments(fp,
&(sb_info[ix][cur_sb_y]), src_rr_node,
&(sb_info[ix - 1][cur_sb_y]), src_rr_node,
rpt_name);
}
} else if ((DEC_DIRECTION == src_rr_node->direction)
&&(CHANY == src_rr_node->type)) {
@ -1285,26 +1334,559 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
for (iy = src_sb_info->y - 1; iy > end_sb_y; iy--) {
/* If this is the ending point, we add a ending segment */
if (iy == end_sb_y + 1) {
verilog_generate_report_timing_one_sb_ending_segments(fp,
&(sb_info[cur_sb_x][iy]), src_rr_node,
des_rr_node,
rpt_name);
continue;
switch (des_rr_node->type) {
case IPIN:
/* Get the coordinate of ending CB */
next_cb = get_chan_rr_node_ending_cb(src_rr_node, des_rr_node);
fprintf(fp, " -to ");
fprintf(fp, "%s/",
gen_verilog_one_cb_instance_name(next_cb));
/* output pin name */
fprintf(fp, "%s",
gen_verilog_routing_channel_one_midout_name( next_cb,
src_rr_node->ptc_num));
fprintf(fp, " -point_to_point");
fprintf(fp, " -unconstrained");
break;
case CHANX:
case CHANY:
/* Get the coordinate of ending SB */
next_sb = get_chan_rr_node_ending_sb(src_rr_node, des_rr_node);
fprintf(fp, " -to ");
fprintf(fp, "%s/",
gen_verilog_one_sb_instance_name(next_sb));
/* Find which side the ending pin locates, and determine the coordinate */
dump_verilog_one_sb_chan_pin(fp, next_sb, src_rr_node, IN_PORT);
fprintf(fp, " -point_to_point");
fprintf(fp, " -unconstrained");
}
}
/* Report timing for the downstream segements, from a SB output to an adjacent CB input */
verilog_generate_report_timing_one_sb_thru_segments(fp,
&(sb_info[cur_sb_x][iy]), src_rr_node,
&(sb_info[cur_sb_x][iy - 1]), src_rr_node,
rpt_name);
}
}
if (NULL != rpt_name) {
fprintf(fp, " > %s\n", rpt_name);
} else {
fprintf(fp, "\n");
}
/* Free */
my_free(rpt_name);
return;
}
///* Print the pins of SBs that a routing wire will go through
// * from the src_rr_node to the des_rr_node
// */
//static
//void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
// t_syn_verilog_opts fpga_verilog_opts,
// const RRGSB& src_sb,
// t_rr_node* drive_rr_node,
// t_rr_node* src_rr_node,
// t_rr_node* des_rr_node,
// int path_cnt) {
// int L_wire;
// int cur_sb_x, cur_sb_y;
// int end_sb_x, end_sb_y;
// t_cb* next_cb = NULL;
// char* rpt_name = NULL;
// DeviceCoordinator next_sb_coordinator;
// RRGSB next_sb;
//
// /* Check the file handler */
// if (NULL == fp) {
// vpr_printf(TIO_MESSAGE_ERROR,
// "(FILE:%s,LINE[%d])Invalid file handler for SDC generation",
// __FILE__, __LINE__);
// exit(1);
// }
//
// /* Check */
// assert ((INC_DIRECTION == src_rr_node->direction)
// ||(DEC_DIRECTION == src_rr_node->direction));
// assert ((CHANX == src_rr_node->type)
// ||(CHANY == src_rr_node->type));
//
// L_wire = get_rr_node_wire_length(src_rr_node);
//
// /* Get report name */
// rpt_name = gen_verilog_one_routing_report_timing_rpt_name(fpga_verilog_opts.report_timing_path,
// L_wire, path_cnt);
//
// /* Start printing report timing info */
// fprintf(fp, "# L%d wire, Path ID: %d\n",
// L_wire,
// path_cnt);
// /* Report timing for the SB MUX delay, from the drive_rr_node to the wire_rr_node */
// verilog_generate_one_report_timing_within_sb(fp, src_sb,
// drive_rr_node,
// src_rr_node);
// if (NULL != rpt_name) {
// fprintf(fp, " > %s\n", rpt_name);
// } else {
// fprintf(fp, "\n");
// }
//
// /* Switch depends on the type of des_rr_node */
// switch(des_rr_node->type) {
// /* Range of SBs that on the path
// * ---------
// * | |
// * | des_sb |
// * | [x][y] |
// * ---------
// * /|\
// * |
// * ---------
// * | |
// * | thru_cb |
// * | |
// * ---------
// * /|\
// * |
// * -------- ------- --------- ------- --------
// * | | | | | | | | | |
// * | des_sb |<---|thru_cb|<---| src_sb |--->|thru_cb|--->| des_sb |
// * |[x-1][y]| | [x][y]| | | | [x][y]| |[x][y] |
// * -------- ------- --------- ------- --------
// * |
// * \|/
// * ---------
// * | |
// * | thru_cb |
// * | |
// * ---------
// * |
// * \|/
// * ---------
// * | |
// * | des_sb |
// * | [x][y-1]|
// * ---------
// */
// case IPIN:
// /* Get the coordinate of ending CB */
// next_cb = get_chan_rr_node_ending_cb(src_rr_node, des_rr_node);
// assert(next_cb->type == src_rr_node->type);
// /* 4 cases: */
// if ((INC_DIRECTION == src_rr_node->direction)
// &&(CHANX == src_rr_node->type)) {
// end_sb_x = next_cb->x;
// end_sb_y = next_cb->y;
// } else if ((INC_DIRECTION == src_rr_node->direction)
// &&(CHANY == src_rr_node->type)) {
// end_sb_x = next_cb->x;
// end_sb_y = next_cb->y;
// } else if ((DEC_DIRECTION == src_rr_node->direction)
// &&(CHANX == src_rr_node->type)) {
// end_sb_x = next_cb->x - 1;
// end_sb_y = next_cb->y;
// } else if ((DEC_DIRECTION == src_rr_node->direction)
// &&(CHANY == src_rr_node->type)) {
// end_sb_x = next_cb->x;
// end_sb_y = next_cb->y - 1;
// }
// break;
// /* Range of SBs that on the path
// * ---------
// * | |
// * | des_sb |
// * | [x][y+1]|
// * ---------
// * /|\
// * |
// * ---------
// * | |
// * | thru_sb |
// * | |
// * ---------
// * /|\
// * |
// * -------- ------- --------- ------- --------
// * | | | | | | | | | |
// * | des_sb |<---|thru_sb|<---| src_sb |--->|thru_sb|--->| des_sb |
// * |[x-1][y]| | [x][y]| | | | [x][y]| |[x+1][y]|
// * -------- ------- --------- ------- --------
// * |
// * \|/
// * ---------
// * | |
// * | thru_sb |
// * | |
// * ---------
// * |
// * \|/
// * ---------
// * | |
// * | des_sb |
// * | [x][y-1]|
// * ---------
// */
// case CHANX:
// case CHANY:
// /* Get the coordinate of ending CB */
// next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
// next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
// end_sb_x = next_sb.get_sb_x();
// end_sb_y = next_sb.get_sb_y();
// break;
// default:
// vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid type of rr_node!\n",
// __FILE__, __LINE__);
// exit(1);
// }
//
// /* Get the base coordinate of src_sb */
// cur_sb_x = src_sb.get_sb_x();
// cur_sb_y = src_sb.get_sb_y();
// /* 4 cases: */
// if ((INC_DIRECTION == src_rr_node->direction)
// &&(CHANX == src_rr_node->type)) {
// /* Follow the graph above, go through X channel */
// for (int ix = src_sb.get_sb_x(); ix < end_sb_x; ix++) {
// DeviceCoordinator begin_sb_coordinator(ix, cur_sb_y);
// RRGSB begin_sb = device_rr_gsb.get_gsb(begin_sb_coordinator);
// /* If this is the ending point, we add a ending segment */
// if (ix == end_sb_x - 1) {
// verilog_generate_report_timing_one_sb_ending_segments(fp,
// begin_sb, src_rr_node,
// des_rr_node,
// rpt_name);
//
// continue;
// }
// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */
// DeviceCoordinator end_sb_coordinator(ix + 1, cur_sb_y);
// RRGSB end_sb = device_rr_gsb.get_gsb(end_sb_coordinator);
// verilog_generate_report_timing_one_sb_thru_segments(fp,
// begin_sb, src_rr_node,
// end_sb, src_rr_node,
// rpt_name);
// }
// } else if ((INC_DIRECTION == src_rr_node->direction)
// &&(CHANY == src_rr_node->type)) {
// /* Follow the graph above, go through Y channel */
// for (int iy = src_sb.get_sb_y(); iy < end_sb_y; iy++) {
// DeviceCoordinator begin_sb_coordinator(cur_sb_x, iy);
// RRGSB begin_sb = device_rr_gsb.get_gsb(begin_sb_coordinator);
// /* If this is the ending point, we add a ending segment */
// if (iy == end_sb_y - 1) {
// verilog_generate_report_timing_one_sb_ending_segments(fp,
// begin_sb, src_rr_node,
// des_rr_node,
// rpt_name);
// continue;
// }
// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */
// DeviceCoordinator end_sb_coordinator(cur_sb_x, iy + 1);
// RRGSB end_sb = device_rr_gsb.get_gsb(end_sb_coordinator);
// verilog_generate_report_timing_one_sb_thru_segments(fp,
// begin_sb, src_rr_node,
// end_sb, src_rr_node,
// rpt_name);
// }
// } else if ((DEC_DIRECTION == src_rr_node->direction)
// &&(CHANX == src_rr_node->type)) {
// /* Follow the graph above, go through X channel */
// for (int ix = src_sb.get_sb_x() - 1; ix > end_sb_x; ix--) {
// DeviceCoordinator begin_sb_coordinator(ix, cur_sb_y);
// RRGSB begin_sb = device_rr_gsb.get_gsb(begin_sb_coordinator);
// /* If this is the ending point, we add a ending segment */
// if (ix == end_sb_x + 1) {
// verilog_generate_report_timing_one_sb_ending_segments(fp,
// begin_sb, src_rr_node,
// des_rr_node,
// rpt_name);
// continue;
// }
// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */
// DeviceCoordinator end_sb_coordinator(ix - 1, cur_sb_y);
// RRGSB end_sb = device_rr_gsb.get_gsb(end_sb_coordinator);
// verilog_generate_report_timing_one_sb_thru_segments(fp,
// begin_sb, src_rr_node,
// end_sb, src_rr_node,
// rpt_name);
// }
// } else if ((DEC_DIRECTION == src_rr_node->direction)
// &&(CHANY == src_rr_node->type)) {
// /* Follow the graph above, go through Y channel */
// for (int iy = src_sb.get_sb_y() - 1; iy > end_sb_y; iy--) {
// DeviceCoordinator begin_sb_coordinator(cur_sb_x, iy);
// RRGSB begin_sb = device_rr_gsb.get_gsb(begin_sb_coordinator);
// /* If this is the ending point, we add a ending segment */
// if (iy == end_sb_y + 1) {
// verilog_generate_report_timing_one_sb_ending_segments(fp,
// begin_sb, src_rr_node,
// des_rr_node,
// rpt_name);
// continue;
// }
// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */
// DeviceCoordinator end_sb_coordinator(cur_sb_x, iy - 1);
// RRGSB end_sb = device_rr_gsb.get_gsb(end_sb_coordinator);
// verilog_generate_report_timing_one_sb_thru_segments(fp,
// begin_sb, src_rr_node,
// end_sb, src_rr_node,
// rpt_name);
// }
// }
//
// /* Free */
// my_free(rpt_name);
//
// return;
//}
//
//
///* Print the pins of SBs that a routing wire will go through
// * from the src_rr_node to the des_rr_node
// */
//static
//void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
// t_syn_verilog_opts fpga_verilog_opts,
// t_sb* src_sb_info,
// t_rr_node* drive_rr_node,
// t_rr_node* src_rr_node,
// t_rr_node* des_rr_node,
// int path_cnt) {
// int L_wire;
// int ix, iy;
// int cur_sb_x, cur_sb_y;
// int end_sb_x, end_sb_y;
// t_cb* next_cb = NULL;
// t_sb* next_sb = NULL;
// char* rpt_name = NULL;
//
// /* Check the file handler */
// if (NULL == fp) {
// vpr_printf(TIO_MESSAGE_ERROR,
// "(FILE:%s,LINE[%d])Invalid file handler for SDC generation",
// __FILE__, __LINE__);
// exit(1);
// }
//
// /* Check */
// assert ((INC_DIRECTION == src_rr_node->direction)
// ||(DEC_DIRECTION == src_rr_node->direction));
// assert ((CHANX == src_rr_node->type)
// ||(CHANY == src_rr_node->type));
//
// L_wire = get_rr_node_wire_length(src_rr_node);
//
// /* Get report name */
// rpt_name = gen_verilog_one_routing_report_timing_rpt_name(fpga_verilog_opts.report_timing_path,
// L_wire, path_cnt);
//
// /* Start printing report timing info */
// fprintf(fp, "# L%d wire, Path ID: %d\n",
// L_wire,
// path_cnt);
// /* Report timing for the SB MUX delay, from the drive_rr_node to the wire_rr_node */
// verilog_generate_one_report_timing_within_sb(fp, src_sb_info,
// drive_rr_node,
// src_rr_node);
// if (NULL != rpt_name) {
// fprintf(fp, " > %s\n", rpt_name);
// } else {
// fprintf(fp, "\n");
// }
//
// /* Switch depends on the type of des_rr_node */
// switch(des_rr_node->type) {
// /* Range of SBs that on the path
// * ---------
// * | |
// * | des_sb |
// * | [x][y] |
// * ---------
// * /|\
// * |
// * ---------
// * | |
// * | thru_cb |
// * | |
// * ---------
// * /|\
// * |
// * -------- ------- --------- ------- --------
// * | | | | | | | | | |
// * | des_sb |<---|thru_cb|<---| src_sb |--->|thru_cb|--->| des_sb |
// * |[x-1][y]| | [x][y]| | | | [x][y]| |[x][y] |
// * -------- ------- --------- ------- --------
// * |
// * \|/
// * ---------
// * | |
// * | thru_cb |
// * | |
// * ---------
// * |
// * \|/
// * ---------
// * | |
// * | des_sb |
// * | [x][y-1]|
// * ---------
// */
// case IPIN:
// /* Get the coordinate of ending CB */
// next_cb = get_chan_rr_node_ending_cb(src_rr_node, des_rr_node);
// assert(next_cb->type == src_rr_node->type);
// /* 4 cases: */
// if ((INC_DIRECTION == src_rr_node->direction)
// &&(CHANX == src_rr_node->type)) {
// end_sb_x = next_cb->x;
// end_sb_y = next_cb->y;
// } else if ((INC_DIRECTION == src_rr_node->direction)
// &&(CHANY == src_rr_node->type)) {
// end_sb_x = next_cb->x;
// end_sb_y = next_cb->y;
// } else if ((DEC_DIRECTION == src_rr_node->direction)
// &&(CHANX == src_rr_node->type)) {
// end_sb_x = next_cb->x - 1;
// end_sb_y = next_cb->y;
// } else if ((DEC_DIRECTION == src_rr_node->direction)
// &&(CHANY == src_rr_node->type)) {
// end_sb_x = next_cb->x;
// end_sb_y = next_cb->y - 1;
// }
// break;
// /* Range of SBs that on the path
// * ---------
// * | |
// * | des_sb |
// * | [x][y+1]|
// * ---------
// * /|\
// * |
// * ---------
// * | |
// * | thru_sb |
// * | |
// * ---------
// * /|\
// * |
// * -------- ------- --------- ------- --------
// * | | | | | | | | | |
// * | des_sb |<---|thru_sb|<---| src_sb |--->|thru_sb|--->| des_sb |
// * |[x-1][y]| | [x][y]| | | | [x][y]| |[x+1][y]|
// * -------- ------- --------- ------- --------
// * |
// * \|/
// * ---------
// * | |
// * | thru_sb |
// * | |
// * ---------
// * |
// * \|/
// * ---------
// * | |
// * | des_sb |
// * | [x][y-1]|
// * ---------
// */
// case CHANX:
// case CHANY:
// /* Get the coordinate of ending CB */
// next_sb = get_chan_rr_node_ending_sb(src_rr_node, des_rr_node);
// end_sb_x = next_sb->x;
// end_sb_y = next_sb->y;
// break;
// default:
// vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid type of rr_node!\n",
// __FILE__, __LINE__);
// exit(1);
// }
//
// /* Get the base coordinate of src_sb */
// cur_sb_x = src_sb_info->x;
// cur_sb_y = src_sb_info->y;
// /* 4 cases: */
// if ((INC_DIRECTION == src_rr_node->direction)
// &&(CHANX == src_rr_node->type)) {
// /* Follow the graph above, go through X channel */
// for (ix = src_sb_info->x; ix < end_sb_x; ix++) {
// /* If this is the ending point, we add a ending segment */
// if (ix == end_sb_x - 1) {
// verilog_generate_report_timing_one_sb_ending_segments(fp,
// &(sb_info[ix][cur_sb_y]), src_rr_node,
// des_rr_node,
// rpt_name);
//
// continue;
// }
// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */
// verilog_generate_report_timing_one_sb_thru_segments(fp,
// &(sb_info[ix][cur_sb_y]), src_rr_node,
// &(sb_info[ix + 1][cur_sb_y]), src_rr_node,
// rpt_name);
// }
// } else if ((INC_DIRECTION == src_rr_node->direction)
// &&(CHANY == src_rr_node->type)) {
// /* Follow the graph above, go through Y channel */
// for (iy = src_sb_info->y; iy < end_sb_y; iy++) {
// /* If this is the ending point, we add a ending segment */
// if (iy == end_sb_y - 1) {
// verilog_generate_report_timing_one_sb_ending_segments(fp,
// &(sb_info[cur_sb_x][iy]), src_rr_node,
// des_rr_node,
// rpt_name);
// continue;
// }
// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */
// verilog_generate_report_timing_one_sb_thru_segments(fp,
// &(sb_info[cur_sb_x][iy]), src_rr_node,
// &(sb_info[cur_sb_x][iy + 1]), src_rr_node,
// rpt_name);
// }
// } else if ((DEC_DIRECTION == src_rr_node->direction)
// &&(CHANX == src_rr_node->type)) {
// /* Follow the graph above, go through X channel */
// for (ix = src_sb_info->x - 1; ix > end_sb_x; ix--) {
// /* If this is the ending point, we add a ending segment */
// if (ix == end_sb_x + 1) {
// verilog_generate_report_timing_one_sb_ending_segments(fp,
// &(sb_info[ix][cur_sb_y]), src_rr_node,
// des_rr_node,
// rpt_name);
// continue;
// }
// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */
// verilog_generate_report_timing_one_sb_thru_segments(fp,
// &(sb_info[ix][cur_sb_y]), src_rr_node,
// &(sb_info[ix - 1][cur_sb_y]), src_rr_node,
// rpt_name);
// }
// } else if ((DEC_DIRECTION == src_rr_node->direction)
// &&(CHANY == src_rr_node->type)) {
// /* Follow the graph above, go through Y channel */
// for (iy = src_sb_info->y - 1; iy > end_sb_y; iy--) {
// /* If this is the ending point, we add a ending segment */
// if (iy == end_sb_y + 1) {
// verilog_generate_report_timing_one_sb_ending_segments(fp,
// &(sb_info[cur_sb_x][iy]), src_rr_node,
// des_rr_node,
// rpt_name);
// continue;
// }
// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */
// verilog_generate_report_timing_one_sb_thru_segments(fp,
// &(sb_info[cur_sb_x][iy]), src_rr_node,
// &(sb_info[cur_sb_x][iy - 1]), src_rr_node,
// rpt_name);
// }
// }
//
// /* Free */
// my_free(rpt_name);
//
// return;
//}
/* Print the pins of SBs that a routing wire will go through
* from the src_rr_node to the des_rr_node
*/
@ -1528,6 +2110,7 @@ void dump_verilog_sb_through_routing_pins(FILE* fp,
}
/* Print the pins of SBs that a routing wire will go through
* from the src_rr_node to the des_rr_node
*/
@ -2298,7 +2881,7 @@ void verilog_generate_one_routing_segmental_report_timing(FILE* fp,
return;
}
//BC TODO
static
void verilog_generate_routing_report_timing(t_trpt_opts trpt_opts,
t_rr_node* LL_rr_node,
@ -2497,3 +3080,4 @@ void verilog_generate_report_timing(t_sram_orgz_info* cur_sram_orgz_info,
return;
}