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OpenFPGA
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev

This commit is contained in:
Baudouin Chauviere 2019-07-10 14:16:55 -06:00
parent 0a978db866 c6a4d29ed8
commit 6441f2ebe7
5 changed files with 39 additions and 15 deletions
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13
vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp
View File

@ -687,10 +687,15 @@ void alloc_rr_graph_fast_lookup(const DeviceCoordinator& device_size,
if ((SOURCE == type) || (OPIN == type) ) {
continue;
}
rr_graph->rr_node_indices[type] = (t_ivec **) my_malloc(sizeof(t_ivec *) * device_size.get_x());
for (size_t i = 0; i < device_size.get_x(); ++i) {
rr_graph->rr_node_indices[type][i] = (t_ivec *) my_malloc(sizeof(t_ivec) * device_size.get_y());
for (size_t j = 0; j < device_size.get_y(); ++j) {
DeviceCoordinator actual_device_size(device_size);
/* Special for CHANX: we use (y,x) in allocation */
if (CHANX == type) {
actual_device_size.rotate();
}
rr_graph->rr_node_indices[type] = (t_ivec **) my_malloc(sizeof(t_ivec *) * actual_device_size.get_x());
for (size_t i = 0; i < actual_device_size.get_x(); ++i) {
rr_graph->rr_node_indices[type][i] = (t_ivec *) my_malloc(sizeof(t_ivec) * actual_device_size.get_y());
for (size_t j = 0; j < actual_device_size.get_y(); ++j) {
rr_graph->rr_node_indices[type][i][j].nelem = 0;
rr_graph->rr_node_indices[type][i][j].list = NULL;
}

29
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c
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@ -1324,6 +1324,10 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir,
clock_t t_end;
float run_time_sec;
clock_t t_start_profiling;
clock_t t_end_profiling;
float run_time_sec_profiling = 0.;
/* Start time count */
t_start = clock();
@ -1338,12 +1342,19 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir,
/* For each switch block, determine the size of array */
for (size_t ix = 0; ix <= sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy <= sb_range.get_y(); ++iy) {
RRGSB rr_gsb = build_rr_gsb(sb_range, ix, iy,
LL_num_rr_nodes, LL_rr_node,
LL_rr_node_indices,
num_segments, LL_rr_indexed_data);
const RRGSB& rr_gsb = build_rr_gsb(sb_range, ix, iy,
LL_num_rr_nodes, LL_rr_node,
LL_rr_node_indices,
num_segments, LL_rr_indexed_data);
/* For profiling */
t_start_profiling = clock();
/* sort drive_rr_nodes */
sort_rr_gsb_drive_rr_nodes(rr_gsb);
/* End time count */
t_end_profiling = clock();
run_time_sec_profiling += (float)(t_end_profiling - t_start_profiling) / CLOCKS_PER_SEC;
/* Add to device_rr_gsb */
DeviceCoordinator sb_coordinator = rr_gsb.get_sb_coordinator();
LL_device_rr_gsb.add_rr_gsb(sb_coordinator, rr_gsb);
@ -1354,6 +1365,14 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir,
"Backannotated %d switch blocks.\n",
(nx + 1) * (ny + 1) );
/* End time count */
t_end = clock();
run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC;
vpr_printf(TIO_MESSAGE_INFO, "Backannotation of Switch Block took %g seconds\n\n", run_time_sec);
vpr_printf(TIO_MESSAGE_INFO, "Edge sorting for Switch Block took %g seconds\n\n", run_time_sec_profiling);
if (TRUE == output_sb_xml) {
create_dir_path(sb_xml_dir);
@ -1406,7 +1425,7 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir,
t_end = clock();
run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC;
vpr_printf(TIO_MESSAGE_INFO, "Routing architecture uniqifying took %g seconds\n", run_time_sec);
vpr_printf(TIO_MESSAGE_INFO, "Routing architecture uniqifying took %g seconds\n\n", run_time_sec);
return LL_device_rr_gsb;
}

4
vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp
View File

@ -2598,7 +2598,7 @@ void DeviceRRGSB::reserve_sb_unique_submodule_id(DeviceCoordinator& coordinator)
}
/* Resize rr_switch_block array is needed*/
void DeviceRRGSB::resize_upon_need(DeviceCoordinator& coordinator) {
void DeviceRRGSB::resize_upon_need(const DeviceCoordinator& coordinator) {
if (coordinator.get_x() + 1 > rr_gsb_.size()) {
rr_gsb_.resize(coordinator.get_x() + 1);
@ -2622,7 +2622,7 @@ void DeviceRRGSB::resize_upon_need(DeviceCoordinator& coordinator) {
}
/* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
void DeviceRRGSB::add_rr_gsb(DeviceCoordinator& coordinator,
void DeviceRRGSB::add_rr_gsb(const DeviceCoordinator& coordinator,
const RRGSB& rr_gsb) {
/* Resize upon needs*/
resize_upon_need(coordinator);

4
vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h
View File

@ -353,8 +353,8 @@ class DeviceRRGSB {
void set_cb_conf_bits_msb(DeviceCoordinator& coordinator, t_rr_type cb_type, size_t conf_bits_msb); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */
void reserve(DeviceCoordinator& coordinator); /* Pre-allocate the rr_switch_block array that the device requires */
void reserve_sb_unique_submodule_id(DeviceCoordinator& coordinator); /* Pre-allocate the rr_sb_unique_module_id matrix that the device requires */
void resize_upon_need(DeviceCoordinator& coordinator); /* Resize the rr_switch_block array if needed */
void add_rr_gsb(DeviceCoordinator& coordinator, const RRGSB& rr_gsb); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
void resize_upon_need(const DeviceCoordinator& coordinator); /* Resize the rr_switch_block array if needed */
void add_rr_gsb(const DeviceCoordinator& coordinator, const RRGSB& rr_gsb); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
void build_unique_module(); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
void clear(); /* clean the content */
private: /* Internal cleaners */

4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
View File

@ -1032,7 +1032,7 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or
/* Get X-channel CB coordinator */
const DeviceCoordinator cbx_coordinator = rr_gsb.get_cb_coordinator(CHANX);
/* X - channels [1...nx][0..ny]*/
if ((TRUE == is_cb_exist(CHANX, cbx_coordinator.get_x(), cbx_coordinator.get_x()))
if ((TRUE == is_cb_exist(CHANX, cbx_coordinator.get_x(), cbx_coordinator.get_y()))
&&(true == rr_gsb.is_cb_exist(CHANX))) {
dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANX, is_explicit_mapping);
}
@ -1040,7 +1040,7 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or
/* Get X-channel CB coordinator */
const DeviceCoordinator cby_coordinator = rr_gsb.get_cb_coordinator(CHANY);
/* Y - channels [1...ny][0..nx]*/
if ((TRUE == is_cb_exist(CHANY, cby_coordinator.get_x(), cby_coordinator.get_x()))
if ((TRUE == is_cb_exist(CHANY, cby_coordinator.get_x(), cby_coordinator.get_y()))
&&(true == rr_gsb.is_cb_exist(CHANY))) {
dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANY, is_explicit_mapping);
}