Add travis full path to avoid missing sources
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@ -10,7 +10,7 @@ modelsim_ini_file="/uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/mode
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# VPR critical inputs
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#set arch_xml_file=ARCH/k6_N10_MD_tsmc40nm_chain_TT.xml
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#set arch_xml_file=ARCH/k8_N10_SC_tsmc40nm_chain_TT_stratixIV_lookalike.xml
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arch_xml_file="ARCH/.regression_k6_N10_sram_chain_HC.xml"
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arch_xml_file="ARCH/.travis_k6_N10_sram_chain_HC.xml"
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#set arch_xml_file=ARCH/ed_stdcell.xml
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#set arch_xml_file=ARCH/k6_N10_sram_chain_FC_tsmc40.xml
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#set arch_xml_file=ARCH/k6_N10_SC_tsmc40nm_chain_TT.xml
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@ -5,7 +5,7 @@
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// Coder : Xifan TANG
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//-----------------------------------------------------
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//------ Include defines: preproc flags -----
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`include "/research/ece/lnis/USERS/alacchi/Current_release/branch_multimode/OpenFPGA/vpr7_x2p/vpr/s298_prevpr_Verilog/SRC/fpga_defines.v"
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`include "/home/travis/build/LNIS-Projects/OpenFPGA/vpr7_x2p/vpr/test_modes_Verilog/SRC/fpga_defines.v"
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module static_dff (
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/* Global ports go first */
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input set, // set input
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