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Add travis full path to avoid missing sources

This commit is contained in:
AurelienUoU 2019-05-16 15:51:10 -06:00
parent 9b28b303b4
commit 4f921b03da
3 changed files with 1042 additions and 2 deletions
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2
vpr7_x2p/vpr/.regression_verilog.sh
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@ -10,7 +10,7 @@ modelsim_ini_file="/uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/mode
# VPR critical inputs
#set arch_xml_file=ARCH/k6_N10_MD_tsmc40nm_chain_TT.xml
#set arch_xml_file=ARCH/k8_N10_SC_tsmc40nm_chain_TT_stratixIV_lookalike.xml
arch_xml_file="ARCH/.regression_k6_N10_sram_chain_HC.xml"
arch_xml_file="ARCH/.travis_k6_N10_sram_chain_HC.xml"
#set arch_xml_file=ARCH/ed_stdcell.xml
#set arch_xml_file=ARCH/k6_N10_sram_chain_FC_tsmc40.xml
#set arch_xml_file=ARCH/k6_N10_SC_tsmc40nm_chain_TT.xml

1040
vpr7_x2p/vpr/ARCH/.travis_k6_N10_sram_chain_HC.xml Normal file
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2
vpr7_x2p/vpr/VerilogNetlists/ff.v
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@ -5,7 +5,7 @@
// Coder : Xifan TANG
//-----------------------------------------------------
//------ Include defines: preproc flags -----
`include "/research/ece/lnis/USERS/alacchi/Current_release/branch_multimode/OpenFPGA/vpr7_x2p/vpr/s298_prevpr_Verilog/SRC/fpga_defines.v"
`include "/home/travis/build/LNIS-Projects/OpenFPGA/vpr7_x2p/vpr/test_modes_Verilog/SRC/fpga_defines.v"
module static_dff (
/* Global ports go first */
input set, // set input