Update ERI-demo
This commit is contained in:
AurelienUoU
parent
1848771e54
commit
e65cf9f5fd
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@ -5,7 +5,7 @@
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my_pwd=$PWD
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fpga_flow_scripts=${my_pwd}/fpga_flow/scripts
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vpr_path=${my_pwd}/vpr7_x2p/vpr
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benchmark="pipelined_8b_adder"
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benchmark="test_modes"
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include_netlists="_include_netlists.v"
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compiled_file="compiled_$benchmark"
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tb_formal_postfix="_top_formal_verification_random_tb"
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@ -45,5 +45,7 @@ if ["$result" = ""]; then
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fi
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else
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echo "Verification succeed"
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cd $my_pwd
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fi
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gtkwave ${benchmark}_formal.vcd &
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cd $my_pwd
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@ -3,18 +3,18 @@
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# Set variables
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# For FPGA-Verilog ONLY
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benchmark="pipelined_8b_adder"
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benchmark="test_modes"
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OpenFPGA_path="OPENFPGAPATHKEYWORD"
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verilog_output_dirname="${benchmark}_Verilog"
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verilog_output_dirpath="$vpr_path"
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tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml"
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# VPR critical inputs
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template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml"
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arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC_DPRAM.xml"
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blif_file="${OpenFPGA_path}/ERI_demo/$benchmark.blif"
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act_file="${OpenFPGA_path}/ERI_demo/$benchmark.act "
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verilog_reference="${OpenFPGA_path}/ERI_demo/$benchmark.v"
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vpr_route_chan_width="300"
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template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml"
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arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml"
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blif_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.blif"
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act_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.act "
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verilog_reference="${OpenFPGA_path}/fpga_flow/benchmarks/Verilog/Test_Modes/$benchmark.v"
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vpr_route_chan_width="200"
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fpga_flow_script="${OpenFPGA_path}/fpga_flow/scripts"
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ff_path="$vpr_path/VerilogNetlists/ff.v"
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new_ff_path="$verilog_output_dirpath/$verilog_output_dirname/SRC/ff.v"
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@ -23,15 +23,13 @@ ff_include_path="$verilog_output_dirpath/$verilog_output_dirname"
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arch_ff_keyword="FFPATHKEYWORD"
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tb_formal_ext="_formal_random_top_tb.v"
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formal_postfix="_top_formal_verification"
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clk_unmapped="clk\[0:0\]"
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clk_mapped="clk_fm"
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# Remove previous designs
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rm -rf $verilog_output_dirpath/$verilog_output_dirname
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mkdir ${OpenFPGA_path}/fpga_flow/arch/generated
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#cd $fpga_flow_scripts
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cd $fpga_flow_scripts
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perl rewrite_path_in_file.pl -i $template_arch_xml_file -o $arch_xml_file
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perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path
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@ -39,14 +37,10 @@ perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path
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cd $vpr_path
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# Run VPR
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./vpr $arch_xml_file $blif_file --full_stats --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --nodisp
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./vpr $arch_xml_file $blif_file --full_stats --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_x2p_compact_routing_hierarchy --fpga_verilog_explicit_mapping --nodisp
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cd $fpga_flow_scripts
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perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path
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rm $verilog_output_dirpath/$verilog_output_dirname/SRC/${benchmark}${tb_formal_ext}
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perl rewrite_path_in_file.pl -i ${OpenFPGA_path}/ERI_demo/${benchmark}${tb_formal_ext} -o $verilog_output_dirpath/$verilog_output_dirname/SRC/${benchmark}${tb_formal_ext}
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cd -
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sed -i 's/^clk\[0:0\]/clk_fm/' $verilog_output_dirpath/$verilog_output_dirname/SRC/${benchmark}${formal_postfix}.v
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@ -1,42 +0,0 @@
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#!/bin/bash
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# Example of how to run vpr
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# Set variables
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# For FPGA-Verilog ONLY
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benchmark="pipelined_32b_adder"
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OpenFPGA_path="/research/ece/lnis/USERS/alacchi/Current_release/branch_multimode/OpenFPGA"
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verilog_output_dirname="${benchmark}_Verilog"
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verilog_output_dirpath="$vpr_path"
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tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml"
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# VPR critical inputs
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template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml"
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arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC_DPRAM.xml"
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blif_file="${OpenFPGA_path}/ERI_demo/$benchmark.blif"
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act_file="${OpenFPGA_path}/ERI_demo/$benchmark.act "
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verilog_reference="${OpenFPGA_path}/ERI_demo/$benchmark.v"
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vpr_route_chan_width="300"
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fpga_flow_script="${OpenFPGA_path}/fpga_flow/scripts"
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ff_path="$vpr_path/VerilogNetlists/ff.v"
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new_ff_path="$verilog_output_dirpath/$verilog_output_dirname/SRC/ff.v"
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ff_keyword="GENERATED_DIR_KEYWORD"
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ff_include_path="$verilog_output_dirpath/$verilog_output_dirname"
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arch_ff_keyword="FFPATHKEYWORD"
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# Remove previous designs
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#rm -rf $verilog_output_dirpath/$verilog_output_dirname
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mkdir ${OpenFPGA_path}/fpga_flow/arch/generated
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cd $fpga_flow_scripts
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perl rewrite_path_in_file.pl -i $template_arch_xml_file -o $arch_xml_file
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perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path
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# Move to vpr folder
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cd $vpr_path
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# Run VPR
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./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator #--fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy
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cd $fpga_flow_scripts
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perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path
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cd -
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@ -1,95 +0,0 @@
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clk 0.5 0.2
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wen 0.5 0.2
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wen_st0 0.5 0.2
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wen_st1 0.5 0.2
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ren 0.5 0.2
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raddr[0] 0.5 0.2
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raddr[1] 0.5 0.2
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raddr[2] 0.5 0.2
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raddr[3] 0.5 0.2
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raddr[4] 0.5 0.2
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raddr[5] 0.5 0.2
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waddr[0] 0.5 0.2
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waddr[1] 0.5 0.2
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waddr[2] 0.5 0.2
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waddr[3] 0.5 0.2
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waddr[4] 0.5 0.2
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waddr[5] 0.5 0.2
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waddr_st0[0] 0.5 0.2
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waddr_st0[1] 0.5 0.2
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waddr_st0[2] 0.5 0.2
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waddr_st0[3] 0.5 0.2
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waddr_st0[4] 0.5 0.2
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waddr_st0[5] 0.5 0.2
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waddr_st1[0] 0.5 0.2
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waddr_st1[1] 0.5 0.2
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waddr_st1[2] 0.5 0.2
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waddr_st1[3] 0.5 0.2
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waddr_st1[4] 0.5 0.2
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waddr_st1[5] 0.5 0.2
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a[0] 0.5 0.2
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a[1] 0.5 0.2
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a[2] 0.5 0.2
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a[3] 0.5 0.2
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a[4] 0.5 0.2
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a[5] 0.5 0.2
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a[6] 0.5 0.2
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a_st0[0] 0.5 0.2
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a_st0[1] 0.5 0.2
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a_st0[2] 0.5 0.2
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a_st0[3] 0.5 0.2
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a_st0[4] 0.5 0.2
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a_st0[5] 0.5 0.2
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a_st0[6] 0.5 0.2
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a_st1[0] 0.5 0.2
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a_st1[1] 0.5 0.2
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a_st1[2] 0.5 0.2
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a_st1[3] 0.5 0.2
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a_st1[4] 0.5 0.2
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a_st1[5] 0.5 0.2
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a_st1[6] 0.5 0.2
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b[0] 0.5 0.2
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b[1] 0.5 0.2
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b[2] 0.5 0.2
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b[3] 0.5 0.2
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b[4] 0.5 0.2
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b[5] 0.5 0.2
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b[6] 0.5 0.2
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b_st0[0] 0.5 0.2
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b_st0[1] 0.5 0.2
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b_st0[2] 0.5 0.2
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b_st0[3] 0.5 0.2
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b_st0[4] 0.5 0.2
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b_st0[5] 0.5 0.2
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b_st0[6] 0.5 0.2
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b_st1[0] 0.5 0.2
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b_st1[1] 0.5 0.2
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b_st1[2] 0.5 0.2
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b_st1[3] 0.5 0.2
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b_st1[4] 0.5 0.2
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b_st1[5] 0.5 0.2
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b_st1[6] 0.5 0.2
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q[0] 0.5 0.2
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q[1] 0.5 0.2
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q[2] 0.5 0.2
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q[3] 0.5 0.2
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q[4] 0.5 0.2
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q[5] 0.5 0.2
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q[6] 0.5 0.2
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q[7] 0.5 0.2
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AplusB[0] 0.5 0.2
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AplusB[1] 0.5 0.2
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AplusB[2] 0.5 0.2
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AplusB[3] 0.5 0.2
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AplusB[4] 0.5 0.2
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AplusB[5] 0.5 0.2
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AplusB[6] 0.5 0.2
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AplusB[7] 0.5 0.2
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cint01 0.5 0.2
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cint02 0.5 0.2
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cint03 0.5 0.2
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cint04 0.5 0.2
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cint05 0.5 0.2
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cint06 0.5 0.2
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cint07 0.5 0.2
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zero00 0 0
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@ -1,137 +0,0 @@
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# Benchmark pipelined_32b_adder
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.model pipelined_32b_adder
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.inputs clk wen ren raddr[0] raddr[1] raddr[2] raddr[3] raddr[4] raddr[5] waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] a[0] a[1] a[2] a[3] a[4] a[5] a[6] b[0] b[1] b[2] b[3] b[4] b[5] b[6]
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.outputs q[0] q[1] q[2] q[3] q[4] q[5] q[6] q[7]
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# Start pipeline
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# Pipeline a
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.subckt shift D=a[0] clk=clk Q=a_st0[0]
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.subckt shift D=a_st0[0] clk=clk Q=a_st1[0]
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.subckt shift D=a[1] clk=clk Q=a_st0[1]
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.subckt shift D=a_st0[1] clk=clk Q=a_st1[1]
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.subckt shift D=a[2] clk=clk Q=a_st0[2]
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.subckt shift D=a_st0[2] clk=clk Q=a_st1[2]
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.subckt shift D=a[3] clk=clk Q=a_st0[3]
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.subckt shift D=a_st0[3] clk=clk Q=a_st1[3]
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.subckt shift D=a[4] clk=clk Q=a_st0[4]
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.subckt shift D=a_st0[4] clk=clk Q=a_st1[4]
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.subckt shift D=a[5] clk=clk Q=a_st0[5]
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.subckt shift D=a_st0[5] clk=clk Q=a_st1[5]
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.subckt shift D=a[6] clk=clk Q=a_st0[6]
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.subckt shift D=a_st0[6] clk=clk Q=a_st1[6]
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# Pipeline b
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.subckt shift D=b[0] clk=clk Q=b_st0[0]
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.subckt shift D=b_st0[0] clk=clk Q=b_st1[0]
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.subckt shift D=b[1] clk=clk Q=b_st0[1]
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.subckt shift D=b_st0[1] clk=clk Q=b_st1[1]
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.subckt shift D=b[2] clk=clk Q=b_st0[2]
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.subckt shift D=b_st0[2] clk=clk Q=b_st1[2]
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.subckt shift D=b[3] clk=clk Q=b_st0[3]
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.subckt shift D=b_st0[3] clk=clk Q=b_st1[3]
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.subckt shift D=b[4] clk=clk Q=b_st0[4]
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.subckt shift D=b_st0[4] clk=clk Q=b_st1[4]
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.subckt shift D=b[5] clk=clk Q=b_st0[5]
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.subckt shift D=b_st0[5] clk=clk Q=b_st1[5]
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.subckt shift D=b[6] clk=clk Q=b_st0[6]
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.subckt shift D=b_st0[6] clk=clk Q=b_st1[6]
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# Pipeline waddr
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.subckt shift D=waddr[0] clk=clk Q=waddr_st0[0]
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.subckt shift D=waddr_st0[0] clk=clk Q=waddr_st1[0]
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.subckt shift D=waddr[1] clk=clk Q=waddr_st0[1]
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.subckt shift D=waddr_st0[1] clk=clk Q=waddr_st1[1]
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.subckt shift D=waddr[2] clk=clk Q=waddr_st0[2]
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.subckt shift D=waddr_st0[2] clk=clk Q=waddr_st1[2]
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.subckt shift D=waddr[3] clk=clk Q=waddr_st0[3]
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.subckt shift D=waddr_st0[3] clk=clk Q=waddr_st1[3]
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.subckt shift D=waddr[4] clk=clk Q=waddr_st0[4]
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.subckt shift D=waddr_st0[4] clk=clk Q=waddr_st1[4]
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.subckt shift D=waddr[5] clk=clk Q=waddr_st0[5]
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.subckt shift D=waddr_st0[5] clk=clk Q=waddr_st1[5]
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# Pipeline wen
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.subckt shift D=wen clk=clk Q=wen_st0
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.subckt shift D=wen_st0 clk=clk Q=wen_st1
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# End pipeline
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# Start adder
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.subckt adder a=a_st1[0] b=b_st1[0] cin=zero00 cout=cint01 sumout=AplusB[0]
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.subckt adder a=a_st1[1] b=b_st1[1] cin=cint01 cout=cint02 sumout=AplusB[1]
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.subckt adder a=a_st1[2] b=b_st1[2] cin=cint02 cout=cint03 sumout=AplusB[2]
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.subckt adder a=a_st1[3] b=b_st1[3] cin=cint03 cout=cint04 sumout=AplusB[3]
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.subckt adder a=a_st1[4] b=b_st1[4] cin=cint04 cout=cint05 sumout=AplusB[4]
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.subckt adder a=a_st1[5] b=b_st1[5] cin=cint05 cout=cint06 sumout=AplusB[5]
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.subckt adder a=a_st1[6] b=b_st1[6] cin=cint06 cout=cint07 sumout=AplusB[6]
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.subckt adder a=zero00 b=zero00 cin=cint07 cout=unconn sumout=AplusB[7]
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# End adder
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# Start DPRAM
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.subckt dpram clk=clk wen=wen_st1 ren=ren \
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waddr[0]=waddr_st1[0] waddr[1]=waddr_st1[1] waddr[2]=waddr_st1[2] waddr[3]=waddr_st1[3] waddr[4]=waddr_st1[4] \
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waddr[5]=waddr_st1[5] waddr[6]=zero00 waddr[7]=zero00 waddr[8]=zero00 waddr[9]=zero00 waddr[10]==zero00 \
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raddr[0]=raddr[0] raddr[1]=raddr[1] raddr[2]=raddr[2] raddr[3]=raddr[3] raddr[4]=raddr[4] raddr[5]=raddr[5] \
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raddr[6]=zero00 raddr[7]=zero00 raddr[8]=zero00 raddr[9]=zero00 raddr[10]=zero00 \
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d_in[0]=AplusB[0] d_in[1]=AplusB[1] d_in[2]=AplusB[2] d_in[3]=AplusB[3] d_in[4]=AplusB[4] d_in[5]=AplusB[5] \
|
||||
d_in[6]=AplusB[6] d_in[7]=AplusB[7] d_in[8]=zero00 d_in[9]=zero00 d_in[10]=zero00 d_in[11]=zero00 \
|
||||
d_in[12]=zero00 d_in[13]=zero00 d_in[14]=zero00 d_in[15]=zero00 d_in[16]=zero00 d_in[17]=zero00 \
|
||||
d_in[18]=zero00 d_in[19]=zero00 d_in[20]=zero00 d_in[21]=zero00 d_in[22]=zero00 d_in[23]=zero00 \
|
||||
d_in[24]=zero00 d_in[25]=zero00 d_in[26]=zero00 d_in[27]=zero00 d_in[28]=zero00 d_in[29]=zero00 \
|
||||
d_in[30]=zero00 d_in[31]=zero00 \
|
||||
d_in[32]=zero00 d_in[33]=zero00 d_in[34]=zero00 d_in[35]=zero00 d_in[36]=zero00 d_in[37]=zero00 d_in[38]=zero00 d_in[39]=zero00 d_in[40]=zero00 d_in[41]=zero00 d_in[42]=zero00 d_in[43]=zero00 d_in[44]=zero00 d_in[45]=zero00 d_in[46]=zero00 d_in[47]=zero00 d_in[48]=zero00 d_in[49]=zero00 d_in[50]=zero00 d_in[51]=zero00 d_in[52]=zero00 d_in[53]=zero00 d_in[54]=zero00 d_in[55]=zero00 d_in[56]=zero00 d_in[57]=zero00 d_in[58]=zero00 d_in[59]=zero00 d_in[60]=zero00 d_in[61]=zero00 d_in[62]=zero00 d_in[63]=zero00 \
|
||||
d_out[0]=q[0] d_out[1]=q[1] d_out[2]=q[2] d_out[3]=q[3] d_out[4]=q[4] d_out[5]=q[5] \
|
||||
d_out[6]=q[6] d_out[7]=q[7] d_out[8]=unconn d_out[9]=unconn d_out[10]=unconn \
|
||||
d_out[11]=unconn d_out[12]=unconn d_out[13]=unconn d_out[14]=unconn d_out[15]=unconn \
|
||||
d_out[16]=unconn d_out[17]=unconn d_out[18]=unconn d_out[19]=unconn d_out[20]=unconn \
|
||||
d_out[21]=unconn d_out[22]=unconn d_out[23]=unconn d_out[24]=unconn d_out[25]=unconn \
|
||||
d_out[26]=unconn d_out[27]=unconn d_out[28]=unconn d_out[29]=unconn d_out[30]=unconn d_out[31]=unconn \
|
||||
d_out[32]=unconn d_out[33]=unconn d_out[34]=unconn d_out[35]=unconn d_out[36]=unconn d_out[37]=unconn d_out[38]=unconn d_out[39]=unconn d_out[40]=unconn d_out[41]=unconn d_out[42]=unconn d_out[43]=unconn d_out[44]=unconn d_out[45]=unconn d_out[46]=unconn d_out[47]=unconn d_out[48]=unconn d_out[49]=unconn d_out[50]=unconn d_out[51]=unconn d_out[52]=unconn d_out[53]=unconn d_out[54]=unconn d_out[55]=unconn d_out[56]=unconn d_out[57]=unconn d_out[58]=unconn d_out[59]=unconn d_out[60]=unconn d_out[61]=unconn d_out[62]=unconn d_out[63]=unconn
|
||||
# End DPRAM
|
||||
|
||||
# Start global variable
|
||||
.names zero00
|
||||
0
|
||||
# End global variable
|
||||
|
||||
|
||||
.end
|
||||
|
||||
# Start blackbox definition
|
||||
.model dpram
|
||||
.inputs clk wen ren waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] \
|
||||
waddr[6] waddr[7] waddr[8] waddr[9] waddr[10] raddr[0] raddr[1] raddr[2] \
|
||||
raddr[3] raddr[4] raddr[5] raddr[6] raddr[7] raddr[8] raddr[9] raddr[10] \
|
||||
d_in[0] d_in[1] d_in[2] d_in[3] d_in[4] d_in[5] d_in[6] d_in[7] d_in[8] \
|
||||
d_in[9] d_in[10] d_in[11] d_in[12] d_in[13] d_in[14] d_in[15] d_in[16] \
|
||||
d_in[17] d_in[18] d_in[19] d_in[20] d_in[21] d_in[22] d_in[23] d_in[24] \
|
||||
d_in[25] d_in[26] d_in[27] d_in[28] d_in[29] d_in[30] d_in[31] d_in[32] \
|
||||
d_in[33] d_in[34] d_in[35] d_in[36] d_in[37] d_in[38] d_in[39] d_in[40] \
|
||||
d_in[41] d_in[42] d_in[43] d_in[44] d_in[45] d_in[46] d_in[47] d_in[48] \
|
||||
d_in[49] d_in[50] d_in[51] d_in[52] d_in[53] d_in[54] d_in[55] d_in[56] \
|
||||
d_in[57] d_in[58] d_in[59] d_in[60] d_in[61] d_in[62] d_in[63]
|
||||
.outputs d_out[0] d_out[1] d_out[2] d_out[3] d_out[4] d_out[5] d_out[6] \
|
||||
d_out[7] d_out[8] d_out[9] d_out[10] d_out[11] d_out[12] d_out[13] \
|
||||
d_out[14] d_out[15] d_out[16] d_out[17] d_out[18] d_out[19] d_out[20] \
|
||||
d_out[21] d_out[22] d_out[23] d_out[24] d_out[25] d_out[26] d_out[27] \
|
||||
d_out[28] d_out[29] d_out[30] d_out[31] d_out[32] d_out[33] d_out[34] \
|
||||
d_out[35] d_out[36] d_out[37] d_out[38] d_out[39] d_out[40] d_out[41] \
|
||||
d_out[42] d_out[43] d_out[44] d_out[45] d_out[46] d_out[47] d_out[48] \
|
||||
d_out[49] d_out[50] d_out[51] d_out[52] d_out[53] d_out[54] d_out[55] \
|
||||
d_out[56] d_out[57] d_out[58] d_out[59] d_out[60] d_out[61] d_out[62] \
|
||||
d_out[63]
|
||||
.blackbox
|
||||
.end
|
||||
|
||||
|
||||
.model adder
|
||||
.inputs a b cin
|
||||
.outputs cout sumout
|
||||
.blackbox
|
||||
.end
|
||||
|
||||
|
||||
.model shift
|
||||
.inputs D clk
|
||||
.outputs Q
|
||||
.blackbox
|
||||
.end
|
||||
# End blackbox definition
|
||||
|
|
@ -1,63 +0,0 @@
|
|||
/////////////////////////////////////
|
||||
// //
|
||||
// ERI summit demo-benchmark //
|
||||
// pipelined_8b_adder.v //
|
||||
// by Aurelien //
|
||||
// //
|
||||
/////////////////////////////////////
|
||||
|
||||
`timescale 1 ns/ 1 ps
|
||||
|
||||
module pipelined_8b_adder(
|
||||
clk,
|
||||
raddr,
|
||||
waddr,
|
||||
ren,
|
||||
wen,
|
||||
a,
|
||||
b,
|
||||
q );
|
||||
|
||||
input clk;
|
||||
input[5:0] raddr;
|
||||
input[5:0] waddr;
|
||||
input ren;
|
||||
input wen;
|
||||
input[6:0] a;
|
||||
input[6:0] b;
|
||||
output[7:0] q;
|
||||
|
||||
reg[63:0] ram[7:0];
|
||||
reg[6:0] a_st0;
|
||||
reg[6:0] a_st1;
|
||||
reg[6:0] b_st0;
|
||||
reg[6:0] b_st1;
|
||||
reg[8:0] waddr_st0;
|
||||
reg[8:0] waddr_st1;
|
||||
reg wen_st0;
|
||||
reg wen_st1;
|
||||
reg[7:0] q_int;
|
||||
|
||||
wire[7:0] AplusB;
|
||||
|
||||
assign AplusB = a_st1 + b_st1;
|
||||
assign q = q_int;
|
||||
|
||||
always@(posedge clk) begin
|
||||
waddr_st0 <= waddr;
|
||||
waddr_st1 <= waddr_st0;
|
||||
a_st0 <= a;
|
||||
a_st1 <= a_st0;
|
||||
b_st0 <= b;
|
||||
b_st1 <= b_st0;
|
||||
wen_st0 <= wen;
|
||||
wen_st1 <= wen_st0;
|
||||
if(wen_st1) begin
|
||||
ram[waddr_st1] <= AplusB;
|
||||
end
|
||||
if(ren) begin
|
||||
q_int <= ram[raddr];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,219 +0,0 @@
|
|||
`timescale 1 ns/ 100 ps
|
||||
|
||||
`include "OPENFPGAPATHKEYWORD/ERI_demo/pipelined_8b_adder.v"
|
||||
|
||||
module pipelined_8b_adder_top_formal_verification_random_tb();
|
||||
reg clk;
|
||||
reg[5:0] raddr;
|
||||
reg[5:0] waddr;
|
||||
reg ren;
|
||||
reg wen;
|
||||
reg[6:0] a;
|
||||
reg[6:0] b;
|
||||
wire[7:0] q_gfpga;
|
||||
wire[7:0] q_bench;
|
||||
reg[7:0] q_flag;
|
||||
|
||||
pipelined_8b_adder_top_formal_verification DUT(
|
||||
.clk_fm (clk),
|
||||
.raddr_0__fm (raddr[0]),
|
||||
.raddr_1__fm (raddr[1]),
|
||||
.raddr_2__fm (raddr[2]),
|
||||
.raddr_3__fm (raddr[3]),
|
||||
.raddr_4__fm (raddr[4]),
|
||||
.raddr_5__fm (raddr[5]),
|
||||
.waddr_0__fm (waddr[0]),
|
||||
.waddr_1__fm (waddr[1]),
|
||||
.waddr_2__fm (waddr[2]),
|
||||
.waddr_3__fm (waddr[3]),
|
||||
.waddr_4__fm (waddr[4]),
|
||||
.waddr_5__fm (waddr[5]),
|
||||
.ren_fm (ren),
|
||||
.wen_fm (wen),
|
||||
.a_0__fm (a[0]),
|
||||
.a_1__fm (a[1]),
|
||||
.a_2__fm (a[2]),
|
||||
.a_3__fm (a[3]),
|
||||
.a_4__fm (a[4]),
|
||||
.a_5__fm (a[5]),
|
||||
.a_6__fm (a[6]),
|
||||
.b_0__fm (b[0]),
|
||||
.b_1__fm (b[1]),
|
||||
.b_2__fm (b[2]),
|
||||
.b_3__fm (b[3]),
|
||||
.b_4__fm (b[4]),
|
||||
.b_5__fm (b[5]),
|
||||
.b_6__fm (b[6]),
|
||||
.out_q_0__fm (q_gfpga[0]),
|
||||
.out_q_1__fm (q_gfpga[1]),
|
||||
.out_q_2__fm (q_gfpga[2]),
|
||||
.out_q_3__fm (q_gfpga[3]),
|
||||
.out_q_4__fm (q_gfpga[4]),
|
||||
.out_q_5__fm (q_gfpga[5]),
|
||||
.out_q_6__fm (q_gfpga[6]),
|
||||
.out_q_7__fm (q_gfpga[7])
|
||||
);
|
||||
|
||||
pipelined_8b_adder ref0(
|
||||
.clk (clk),
|
||||
.raddr (raddr),
|
||||
.waddr (waddr),
|
||||
.ren (ren),
|
||||
.wen (wen),
|
||||
.a (a),
|
||||
.b (b),
|
||||
.q (q_bench)
|
||||
);
|
||||
|
||||
integer nb_error = 0;
|
||||
integer count = 0;
|
||||
integer lim_max = 64 - 1;
|
||||
integer write_complete = 0;
|
||||
|
||||
//----- Initialization
|
||||
initial begin
|
||||
clk <= 1'b0;
|
||||
a <= 7'h00;
|
||||
b <= 7'h00;
|
||||
wen <= 1'b0;
|
||||
ren <= 1'b0;
|
||||
waddr <= 9'h000;
|
||||
raddr <= 9'h000;
|
||||
while(1) begin
|
||||
#2.5
|
||||
clk <= !clk;
|
||||
end
|
||||
end
|
||||
|
||||
//----- Input Stimulis
|
||||
always@(negedge clk) begin
|
||||
if(write_complete == 0) begin
|
||||
wen <= 1'b1;
|
||||
ren <= 1'b0;
|
||||
count <= count + 1;
|
||||
waddr <= waddr + 1;
|
||||
if(count == lim_max) begin
|
||||
write_complete = 1;
|
||||
end
|
||||
end else begin
|
||||
wen <= $random;
|
||||
ren <= $random;
|
||||
waddr <= $random;
|
||||
raddr <= $random;
|
||||
end
|
||||
a <= $random;
|
||||
b <= $random;
|
||||
end
|
||||
|
||||
|
||||
always@(negedge clk) begin
|
||||
if(!(q_gfpga[0] === q_bench[0]) && !(q_bench[0] === 1'bx)) begin
|
||||
q_flag[0] <= 1'b1;
|
||||
end else begin
|
||||
q_flag[0] <= 1'b0;
|
||||
end
|
||||
if(!(q_gfpga[1] === q_bench[1]) && !(q_bench[1] === 1'bx)) begin
|
||||
q_flag[1] <= 1'b1;
|
||||
end else begin
|
||||
q_flag[1] <= 1'b0;
|
||||
end
|
||||
if(!(q_gfpga[2] === q_bench[2]) && !(q_bench[2] === 1'bx)) begin
|
||||
q_flag[2] <= 1'b1;
|
||||
end else begin
|
||||
q_flag[2] <= 1'b0;
|
||||
end
|
||||
if(!(q_gfpga[3] === q_bench[3]) && !(q_bench[3] === 1'bx)) begin
|
||||
q_flag[3] <= 1'b1;
|
||||
end else begin
|
||||
q_flag[3] <= 1'b0;
|
||||
end
|
||||
if(!(q_gfpga[4] === q_bench[4]) && !(q_bench[4] === 1'bx)) begin
|
||||
q_flag[4] <= 1'b1;
|
||||
end else begin
|
||||
q_flag[4] <= 1'b0;
|
||||
end
|
||||
if(!(q_gfpga[5] === q_bench[5]) && !(q_bench[5] === 1'bx)) begin
|
||||
q_flag[5] <= 1'b1;
|
||||
end else begin
|
||||
q_flag[5] <= 1'b0;
|
||||
end
|
||||
if(!(q_gfpga[6] === q_bench[6]) && !(q_bench[6] === 1'bx)) begin
|
||||
q_flag[6] <= 1'b1;
|
||||
end else begin
|
||||
q_flag[6] <= 1'b0;
|
||||
end
|
||||
if(!(q_gfpga[7] === q_bench[7]) && !(q_bench[7] === 1'bx)) begin
|
||||
q_flag[7] <= 1'b1;
|
||||
end else begin
|
||||
q_flag[7] <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge q_flag[0]) begin
|
||||
if(q_flag[0]) begin
|
||||
nb_error = nb_error + 1;
|
||||
$display("Mismatch on q_gfpga[0] at time = %t", $realtime);
|
||||
end
|
||||
end
|
||||
always@(posedge q_flag[1]) begin
|
||||
if(q_flag[1]) begin
|
||||
nb_error = nb_error + 1;
|
||||
$display("Mismatch on q_gfpga[1] at time = %t", $realtime);
|
||||
end
|
||||
end
|
||||
always@(posedge q_flag[2]) begin
|
||||
if(q_flag[2]) begin
|
||||
nb_error = nb_error + 1;
|
||||
$display("Mismatch on q_gfpga[2] at time = %t", $realtime);
|
||||
end
|
||||
end
|
||||
always@(posedge q_flag[3]) begin
|
||||
if(q_flag[3]) begin
|
||||
nb_error = nb_error + 1;
|
||||
$display("Mismatch on q_gfpga[3] at time = %t", $realtime);
|
||||
end
|
||||
end
|
||||
always@(posedge q_flag[4]) begin
|
||||
if(q_flag[4]) begin
|
||||
nb_error = nb_error + 1;
|
||||
$display("Mismatch on q_gfpga[4] at time = %t", $realtime);
|
||||
end
|
||||
end
|
||||
always@(posedge q_flag[5]) begin
|
||||
if(q_flag[5]) begin
|
||||
nb_error = nb_error + 1;
|
||||
$display("Mismatch on q_gfpga[5] at time = %t", $realtime);
|
||||
end
|
||||
end
|
||||
always@(posedge q_flag[6]) begin
|
||||
if(q_flag[6]) begin
|
||||
nb_error = nb_error + 1;
|
||||
$display("Mismatch on q_gfpga[6] at time = %t", $realtime);
|
||||
end
|
||||
end
|
||||
always@(posedge q_flag[7]) begin
|
||||
if(q_flag[7]) begin
|
||||
nb_error = nb_error + 1;
|
||||
$display("Mismatch on q_gfpga[7] at time = %t", $realtime);
|
||||
end
|
||||
end
|
||||
|
||||
initial begin
|
||||
$dumpfile("pipelined_8b_adder_formal.vcd");
|
||||
$dumpvars(1, pipelined_8b_adder_top_formal_verification_random_tb);
|
||||
end
|
||||
|
||||
initial begin
|
||||
$timeformat(-9, 2, "ns", 20);
|
||||
$display("Simulation start");
|
||||
#1500 // Can be changed by the user for his need
|
||||
if(nb_error == 0) begin
|
||||
$display("Simulation Succeed");
|
||||
end else begin
|
||||
$display("Simulation Failed with %d error(s)", nb_error);
|
||||
end
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -28,6 +28,6 @@ perl rewrite_path_in_file.pl -i $ff_path -k $dir_keyword $verilog_path # Set the
|
|||
|
||||
# SRAM FPGA
|
||||
# TT case
|
||||
perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power -vpr_fpga_verilog_print_user_defined_template -vpr_fpga_verilog_print_report_timing_tcl -vpr_fpga_verilog_print_sdc_pnr -vpr_fpga_verilog_print_sdc_analysis -vpr_fpga_x2p_compact_routing_hierarchy -end_flow_with_test -vpr_fpga_verilog_explicit_mapping
|
||||
perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power -vpr_fpga_verilog_print_user_defined_template -vpr_fpga_verilog_print_report_timing_tcl -vpr_fpga_verilog_print_sdc_pnr -vpr_fpga_verilog_print_sdc_analysis -vpr_fpga_x2p_compact_routing_hierarchy -end_flow_with_test -vpr_fpga_verilog_explicit_mapping -vpr_fpga_x2p_compact_routing_hierarchy
|
||||
|
||||
echo "Netlists successfully generated and tested"
|
||||
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|
|
|||
|
|
@ -33,7 +33,7 @@ perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path
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|||
cd -
|
||||
|
||||
# Run VPR
|
||||
./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy --fpga_verilog_explicit_mapping
|
||||
./vpr $arch_xml_file $blif_file --full_stats --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy --fpga_verilog_explicit_mapping
|
||||
|
||||
cd $fpga_flow_scripts
|
||||
perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path
|
||||
|
|
|
|||
Loading…
Reference in New Issue