64 lines
1.0 KiB
Verilog
64 lines
1.0 KiB
Verilog
/////////////////////////////////////
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// //
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// ERI summit demo-benchmark //
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// pipelined_8b_adder.v //
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// by Aurelien //
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// //
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/////////////////////////////////////
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`timescale 1 ns/ 1 ps
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module pipelined_8b_adder(
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clk,
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raddr,
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waddr,
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ren,
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wen,
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a,
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b,
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q );
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input clk;
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input[5:0] raddr;
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input[5:0] waddr;
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input ren;
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input wen;
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input[6:0] a;
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input[6:0] b;
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output[7:0] q;
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reg[63:0] ram[7:0];
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reg[6:0] a_st0;
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reg[6:0] a_st1;
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reg[6:0] b_st0;
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reg[6:0] b_st1;
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reg[8:0] waddr_st0;
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reg[8:0] waddr_st1;
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reg wen_st0;
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reg wen_st1;
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reg[7:0] q_int;
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wire[7:0] AplusB;
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assign AplusB = a_st1 + b_st1;
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assign q = q_int;
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always@(posedge clk) begin
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waddr_st0 <= waddr;
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waddr_st1 <= waddr_st0;
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a_st0 <= a;
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a_st1 <= a_st0;
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b_st0 <= b;
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b_st1 <= b_st0;
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wen_st0 <= wen;
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wen_st1 <= wen_st0;
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if(wen_st1) begin
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ram[waddr_st1] <= AplusB;
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end
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if(ren) begin
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q_int <= ram[raddr];
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end
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end
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endmodule
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