Add forgottent files + add parameter transmission from verilog_api.c
This commit is contained in:
Aur??Lien ALACCHI
parent
9a8c7b391a
commit
dc4accedd9
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@ -251,7 +251,9 @@ void vpr_dump_syn_verilog(t_vpr_setup vpr_setup,
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if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_modelsim_autodeck) {
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dump_verilog_modelsim_autodeck(sram_verilog_orgz_info, *(Arch.spice), num_clocks,
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verilog_dir_formatted, chomped_circuit_name,
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vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.modelsim_ini_path);
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vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.modelsim_ini_path,
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vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.include_timing,
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vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.init_sim);
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}
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/* dump verilog testbench only for input blif */
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@ -0,0 +1,343 @@
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/***********************************/
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/* Synthesizable Verilog Dumping */
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/* Xifan TANG, EPFL/LSI */
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/***********************************/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <math.h>
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#include <time.h>
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#include <assert.h>
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#include <sys/stat.h>
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#include <unistd.h>
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/* Include vpr structs*/
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#include "util.h"
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#include "physical_types.h"
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#include "vpr_types.h"
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#include "globals.h"
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#include "rr_graph.h"
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#include "vpr_utils.h"
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#include "path_delay.h"
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#include "stats.h"
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/* Include FPGA-SPICE utils */
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#include "linkedlist.h"
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#include "fpga_spice_utils.h"
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#include "fpga_spice_globals.h"
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/* Include verilog utils */
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#include "verilog_global.h"
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#include "verilog_utils.h"
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/***** Subroutines *****/
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/* Return the float number of the time unit required by Modelsim */
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float convert_modelsim_time_unit_to_float(char* modelsim_time_unit) {
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/* switch cases is made for s, ms, us, ns, ps and fs*/
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if (0 == strcmp("s", modelsim_time_unit)) {
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return 1;
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} else if (0 == strcmp("ms", modelsim_time_unit)) {
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return 1e-3;
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} else if (0 == strcmp("us", modelsim_time_unit)) {
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return 1e-6;
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} else if (0 == strcmp("ns", modelsim_time_unit)) {
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return 1e-9;
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} else if (0 == strcmp("ps", modelsim_time_unit)) {
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return 1e-12;
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} else if (0 == strcmp("fs", modelsim_time_unit)) {
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return 1e-15;
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} else {
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vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid time unit(=%s) for modelsim!\n",
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__FILE__, __LINE__, modelsim_time_unit);
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exit(1);
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return 0.;
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}
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return 0.;
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}
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static
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void modelsim_include_user_defined_verilog_netlists(FILE* fp,
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t_spice spice) {
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int i;
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/* A valid file handler*/
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if (NULL == fp) {
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vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__);
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exit(1);
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}
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/* Include user-defined sub-circuit netlist */
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for (i = 0; i < spice.num_include_netlist; i++) {
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if (0 == spice.include_netlists[i].included) {
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assert(NULL != spice.include_netlists[i].path);
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fprintf(fp, " %s \\\n", spice.include_netlists[i].path);
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spice.include_netlists[i].included = 1;
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} else {
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assert(1 == spice.include_netlists[i].included);
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}
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}
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return;
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}
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/* Estimate the simulation time period to be assigned in Modelsim:
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* Total simulation time = number of programming clock cycles * programming clock period
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* + number of operating clock cycles * operating clock period
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*/
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float get_verilog_modelsim_simulation_time_period(float time_unit,
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int num_prog_clock_cycles,
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float prog_clock_period,
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int num_op_clock_cycles,
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float op_clock_period) {
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float total_time_period = 0.;
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/* Take into account the prog_reset and reset cycles */
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total_time_period = (num_prog_clock_cycles + 2) * prog_clock_period + num_op_clock_cycles * op_clock_period;
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total_time_period = total_time_period / time_unit;
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return total_time_period;
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}
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void dump_verilog_modelsim_proc_script(char* modelsim_proc_filename,
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char* modelsim_ini_path,
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char* circuit_name,
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boolean include_timing,
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boolean init_sim) {
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FILE* fp = NULL;
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char* circuit_top_tb_name = NULL;
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circuit_top_tb_name = my_strcat(circuit_name, modelsim_testbench_module_postfix);
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/* Create Modelsim proc file */
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/* Open file and file handler */
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fp = fopen(modelsim_proc_filename, "w");
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if (NULL == fp) {
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vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create Modelsim simulation deck auto-generation scripts: %s",
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__FILE__, __LINE__, modelsim_proc_filename);
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exit(1);
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}
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fprintf(fp, "proc create_project {projectname project_path} {\n");
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fprintf(fp, " #Switch to the modelsim folder to create the project\n");
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fprintf(fp, " set libname $projectname\n");
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fprintf(fp, " set initfile %s\n", modelsim_ini_path);
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fprintf(fp, " project new $project_path/$projectname $projectname $libname $initfile 0\n");
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fprintf(fp, "}\n");
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fprintf(fp, " \n");
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fprintf(fp, "proc create_project_with_close {projectname modelsim_path} {\n");
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fprintf(fp, " #Get the current project name\n");
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fprintf(fp, " set project_env [project env]\n");
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fprintf(fp, " if {$project_env eq \"\"} {\n");
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fprintf(fp, " #If string empty (no project)\n");
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fprintf(fp, " create_project $projectname $modelsim_path\n");
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fprintf(fp, " } else {\n");
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fprintf(fp, " #If string not empty (a project is loaded so clsoe it first)\n");
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fprintf(fp, " project close\n");
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fprintf(fp, " create_project $projectname $modelsim_path\n");
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fprintf(fp, " }\n");
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fprintf(fp, " }\n");
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fprintf(fp, " \n");
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fprintf(fp, "proc add_files_project {verilog_files} {\n");
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fprintf(fp, " #Get the length of the list\n");
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fprintf(fp, " set listlength [llength $verilog_files]\n");
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fprintf(fp, " #Add the verilog files one by one\n");
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fprintf(fp, " for {set x 0} {$x<$listlength} {incr x} {\n");
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fprintf(fp, " project addfile [lindex $verilog_files $x]\n");
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fprintf(fp, " }\n");
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fprintf(fp, "}\n");
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fprintf(fp, " \n");
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fprintf(fp, "proc add_waves {} {\n");
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fprintf(fp, " add wave -position insertpoint sim:/%s/*\n", circuit_top_tb_name);
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fprintf(fp, "}\n");
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fprintf(fp, "proc runsim {simtime unit} {\n");
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fprintf(fp, " run $simtime $unit\n");
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fprintf(fp, "}\n");
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fprintf(fp, "#Top procedure to create enw project\n");
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fprintf(fp, "proc top_create_new_project {projectname verilog_files modelsim_path simtime unit} {\n");
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fprintf(fp, " #Create the project\n");
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fprintf(fp, " create_project_with_close $projectname $modelsim_path\n");
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fprintf(fp, " #Add the verilog files\n");
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fprintf(fp, " add_files_project $verilog_files\n");
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fprintf(fp, " #Compile all the files\n");
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// fprintf(fp, " project compileall\n"); // removed to allow compilation with define
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// Begin of compilation with Define
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fprintf(fp, " set myFiles [project filenames]\n");
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fprintf(fp, " foreach x $myFiles {\n");
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fprintf(fp, " vlog ");
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if(TRUE == include_timing){
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fprintf(fp, "+define+%s ", verilog_timing_preproc_flag);
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}
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if(TRUE == init_sim){
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fprintf(fp, "+define+%s ", verilog_init_sim_preproc_flag);
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}
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fprintf(fp, "$x\n }\n");
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// End of compilation with Define
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fprintf(fp, " #Start the simulation\n");
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fprintf(fp, " vsim $projectname.%s -novopt\n", circuit_top_tb_name);
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fprintf(fp, " #Add the waves \n");
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fprintf(fp, " add_waves\n");
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fprintf(fp, " #run the simulation\n");
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fprintf(fp, " runsim $simtime $unit\n");
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fprintf(fp, " #Fit the window view\n");
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fprintf(fp, " wave zoom full\n");
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fprintf(fp, "}\n");
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fprintf(fp, "#Top proc to recompile files and re run the simulation\n");
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fprintf(fp, "proc top_rerun_sim {simtime unit} {\n");
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fprintf(fp, " #Compile updated verilog files\n");
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fprintf(fp, " project compileoutofdate\n");
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fprintf(fp, " #restart the simulation\n");
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fprintf(fp, " restart -force\n");
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fprintf(fp, " #run the simulation\n");
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fprintf(fp, " runsim $simtime $unit\n");
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fprintf(fp, " #Fit the window view\n");
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fprintf(fp, " wave zoom full\n");
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fprintf(fp, "}\n");
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/* Close File handler */
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fclose(fp);
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/* Free */
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my_free(circuit_top_tb_name);
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return;
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}
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void dump_verilog_modelsim_top_script(char* modelsim_top_script_filename,
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char* modelsim_proc_script_filename,
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char* modelsim_project_path,
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char* circuit_name,
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char* modelsim_project_name,
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float sim_time,
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char* sim_time_unit,
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t_spice spice) {
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FILE* fp = NULL;
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/* Create Modelsim proc file */
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/* Open file and file handler */
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fp = fopen(modelsim_top_script_filename, "w");
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if (NULL == fp) {
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vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create Modelsim simulation deck auto-generation scripts: %s",
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__FILE__, __LINE__, modelsim_top_script_filename);
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exit(1);
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}
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fprintf(fp, "set projectname %s\n", modelsim_project_name);
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fprintf(fp, "set benchmark %s\n", circuit_name);
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fprintf(fp, "\n");
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fprintf(fp, "#in ms\n");
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fprintf(fp, "set simtime %.4g\n", sim_time);
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fprintf(fp, "set unit %s\n",
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sim_time_unit);
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fprintf(fp, "\n");
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fprintf(fp, "#Path were both tcl script are located\n");
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fprintf(fp, "set project_path \"%s%s\"\n", modelsim_project_path, default_modelsim_dir_name);
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fprintf(fp, "\n");
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fprintf(fp, "#Path were the verilog files are located\n");
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fprintf(fp, "set verilog_path \"%s\"\n", modelsim_project_path);
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fprintf(fp, "set verilog_files [list \\\n");
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/* TODO: include verilog files */
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fprintf(fp, " ${verilog_path}${benchmark}%s \\\n",
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verilog_top_postfix);
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fprintf(fp, " ${verilog_path}${benchmark}%s \\\n",
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top_testbench_verilog_file_postfix);
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/* User-defined verilog netlists */
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init_include_user_defined_verilog_netlists(spice);
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modelsim_include_user_defined_verilog_netlists(fp, spice);
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fprintf(fp, " ${verilog_path}%s%s \\\n",
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default_lb_dir_name, logic_block_verilog_file_name);
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fprintf(fp, " ${verilog_path}%s%s \\\n",
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default_rr_dir_name, routing_verilog_file_name);
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fprintf(fp, " ${verilog_path}%s%s ] \n",
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default_submodule_dir_name, submodule_verilog_file_name);
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fprintf(fp, "\n");
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fprintf(fp, "#Source the tcl script\n");
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fprintf(fp, "source ${verilog_path}%s\n", modelsim_proc_script_filename);
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fprintf(fp, "\n");
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fprintf(fp, "#Execute the top level procedure\n");
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fprintf(fp, "top_create_new_project $projectname $verilog_files $project_path $simtime $unit\n");
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fprintf(fp, "\n");
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fprintf(fp, "#Relaunch simulation\n");
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/* Close File handler */
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fclose(fp);
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return;
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}
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/***** Top-level function *****/
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void dump_verilog_modelsim_autodeck(t_sram_orgz_info* cur_sram_orgz_info,
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t_spice spice,
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int num_operating_clock_cycles,
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char* verilog_dir_formatted,
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char* chomped_circuit_name,
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char* simulator_ini_path,
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boolean include_timing,
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boolean init_sim) {
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char* modelsim_project_name = NULL;
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char* modelsim_proc_script_filename = NULL;
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char* modelsim_top_script_filename = NULL;
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float simulation_time_period = 0.;
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/* Determine the project name for Modelsim */
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modelsim_project_name = my_strcat(chomped_circuit_name, modelsim_project_name_postfix);
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modelsim_top_script_filename = my_strcat(verilog_dir_formatted, my_strcat(chomped_circuit_name, modelsim_top_script_name_postfix));
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modelsim_proc_script_filename = my_strcat(verilog_dir_formatted, my_strcat(chomped_circuit_name, modelsim_proc_script_name_postfix));
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/* Generate files */
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vpr_printf(TIO_MESSAGE_INFO, "Writing Modelsim simulation deck auto-generation scripts...\n");
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/* Check */
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/* Modelsim ini path must be valid!*/
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if (NULL == simulator_ini_path) {
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vpr_printf(TIO_MESSAGE_INFO, "(FILE:%s, [LINE%d])Invalid Modelsim ini path!\n",
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__FILE__, __LINE__);
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exit(1);
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}
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/* Dump the Modelsim process function file */
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dump_verilog_modelsim_proc_script(modelsim_proc_script_filename,
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simulator_ini_path, chomped_circuit_name,
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include_timing, init_sim);
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/* Compute simulation time period */
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simulation_time_period = get_verilog_modelsim_simulation_time_period(convert_modelsim_time_unit_to_float(modelsim_simulation_time_unit),
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get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info),
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1./spice.spice_params.stimulate_params.prog_clock_freq,
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num_operating_clock_cycles,
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1./spice.spice_params.stimulate_params.op_clock_freq);
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/* Dump the Modelsim top-level script file */
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dump_verilog_modelsim_top_script(modelsim_top_script_filename,
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my_strcat(chomped_circuit_name, modelsim_proc_script_name_postfix),
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verilog_dir_formatted,
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chomped_circuit_name, modelsim_project_name,
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simulation_time_period, modelsim_simulation_time_unit,
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spice);
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/* Free */
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my_free(modelsim_project_name);
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my_free(modelsim_proc_script_filename);
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my_free(modelsim_top_script_filename);
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return;
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}
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@ -0,0 +1,9 @@
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void dump_verilog_modelsim_autodeck(t_sram_orgz_info* cur_sram_orgz_info,
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t_spice spice,
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int num_operating_clock_cycles,
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char* verilog_dir_formatted,
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char* chomped_circuit_name,
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char* simulator_ini_path,
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boolean include_timing,
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boolean init_sim);
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