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Add process for modelsim script autogeneration

This commit is contained in:
Aur??Lien ALACCHI 2018-12-05 09:20:47 -07:00
parent 75d64db0f9
commit 9a8c7b391a
11 changed files with 65 additions and 8 deletions
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9
vpr7_x2p/vpr/SRC/base/OptionTokens.c
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@ -76,14 +76,19 @@ struct s_TokenPair OptionBaseTokenList[] = {
{ "fpga_spice_leakage_only", OT_FPGA_SPICE_LEAKAGE_ONLY }, /* Only simulate leakage power in FPGA SPICE */
{ "fpga_spice_parasitic_net_estimation_off", OT_FPGA_SPICE_PARASITIC_NET_ESTIMATION_OFF }, /* Xifan TANG: turn off the parasitic net estimation*/
{ "fpga_spice_testbench_load_extraction_off", OT_FPGA_SPICE_TESTBENCH_LOAD_EXTRACTION_OFF }, /* Xifan TANG: turn off the parasitic net estimation*/
{ "fpga_verilog_include_timing", OT_FPGA_VERILOG_SYN_INCLUDE_TIMING }, /* Include timing constraints in Verilog netlists */
{ "fpga_verilog_init_sim", OT_FPGA_VERILOG_INIT_SIM }, /* Allow simulation initialization */
/* Xifan TANG: Synthsizable Verilog */
{ "fpga_verilog", OT_FPGA_VERILOG_SYN },
{ "fpga_verilog_dir", OT_FPGA_VERILOG_SYN_DIR },
{ "fpga_verilog_print_top_testbench", OT_FPGA_VERILOG_SYN_PRINT_TOP_TB },
{ "fpga_verilog_print_input_blif_testbench", OT_FPGA_VERILOG_SYN_PRINT_INPUT_BLIF_TB },
{ "fpga_verilog_tb_serial_config_mode", OT_FPGA_VERILOG_SYN_TB_SERIAL_CONFIG_MODE },
{ "fpga_verilog_include_timing", OT_FPGA_VERILOG_SYN_INCLUDE_TIMING }, /* Include timing constraints in Verilog netlists */
{ "fpga_verilog_init_sim", OT_FPGA_VERILOG_INIT_SIM }, /* Allow simulation initialization */
{ "fpga_verilog_print_modelsim_autodeck", OT_FPGA_VERILOG_SYN_PRINT_MODELSIM_AUTODECK }, /* Allow simulation script generation */
{ "fpga_verilog_modelsim_ini_path", OT_FPGA_VERILOG_SYN_MODELSIM_INI_PATH }, /* Specify the simulator path for Verilog netlists */
/* mrFPGA: Xifan TANG */
/* mrFPGA: Xifan TANG */
{"show_sram", OT_SHOW_SRAM},
{"show_pass_trans", OT_SHOW_PASS_TRANS},

2
vpr7_x2p/vpr/SRC/base/OptionTokens.h
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@ -101,6 +101,8 @@ enum e_OptionBaseToken {
OT_FPGA_VERILOG_SYN_TB_SERIAL_CONFIG_MODE, /* Xifan TANG: Synthesizable Verilog Dump */
OT_FPGA_VERILOG_SYN_INCLUDE_TIMING, /* Include timing constraint in Verilog*/
OT_FPGA_VERILOG_INIT_SIM, /* AA: to allow initialization in simulation */
OT_FPGA_VERILOG_SYN_PRINT_MODELSIM_AUTODECK, // To allow modelsim script generation
OT_FPGA_VERILOG_SYN_MODELSIM_INI_PATH, // To set modelsim script path
/* mrFPGA: Xifan TANG */
OT_SHOW_SRAM,
OT_SHOW_PASS_TRANS,

4
vpr7_x2p/vpr/SRC/base/ReadOptions.c
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@ -520,6 +520,10 @@ ProcessOption(INP char **Args, INOUTP t_options * Options) {
return Args;
case OT_FPGA_VERILOG_INIT_SIM:
return Args;
case OT_FPGA_VERILOG_SYN_PRINT_MODELSIM_AUTODECK:
return Args;
case OT_FPGA_VERILOG_SYN_MODELSIM_INI_PATH:
return ReadString(Args, &Options->fpga_verilog_modelsim_ini_path);
case OT_FPGA_SPICE_SIGNAL_DENSITY_WEIGHT:
return ReadFloat(Args, &Options->signal_density_weight);
case OT_FPGA_SPICE_SIM_WINDOW_SIZE:

1
vpr7_x2p/vpr/SRC/base/ReadOptions.h
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@ -95,6 +95,7 @@ struct s_options {
char* spice_dir;
/* Xifan TANG: Synthesizable Verilog */
char* syn_verilog_dir;
char* fpga_verilog_modelsim_ini_path;
/* Xifan TANG: signal weight in FPGA_SPICE simulation */
float signal_density_weight;
float sim_window_size;

12
vpr7_x2p/vpr/SRC/base/SetupVPR.c
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@ -1061,6 +1061,10 @@ static void SetupSynVerilogOpts(t_options Options,
syn_verilog_opts->print_input_blif_tb = FALSE;
syn_verilog_opts->include_timing = FALSE;
syn_verilog_opts->init_sim = FALSE;
syn_verilog_opts->print_modelsim_autodeck = FALSE;
syn_verilog_opts->modelsim_ini_path = NULL;
/* Turn on Syn_verilog options */
if (Options.Count[OT_FPGA_VERILOG_SYN]) {
@ -1093,6 +1097,14 @@ static void SetupSynVerilogOpts(t_options Options,
syn_verilog_opts->init_sim = TRUE;
}
if (Options.Count[OT_FPGA_VERILOG_SYN_PRINT_MODELSIM_AUTODECK]) {
syn_verilog_opts->print_modelsim_autodeck = TRUE;
}
if (Options.Count[OT_FPGA_VERILOG_SYN_MODELSIM_INI_PATH]) {
syn_verilog_opts->modelsim_ini_path = my_strdup(Options.fpga_verilog_modelsim_ini_path);
}
/* SynVerilog needs the input from spice modeling */
if (FALSE == arch->read_xml_spice) {
arch->read_xml_spice = syn_verilog_opts->dump_syn_verilog;

2
vpr7_x2p/vpr/SRC/base/vpr_api.c
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@ -191,6 +191,8 @@ void vpr_print_usage(void) {
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_dir <directory_path_of_dumped_verilog_files>\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_include_timing\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_init_sim\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_modelsim_autodeck\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_modelsim_ini_path <string>\n");
}
/* Initialize VPR

2
vpr7_x2p/vpr/SRC/base/vpr_types.h
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@ -1211,6 +1211,8 @@ struct s_syn_verilog_opts {
boolean tb_serial_config_mode;
boolean include_timing;
boolean init_sim;
boolean print_modelsim_autodeck;
char* modelsim_ini_path;
};
typedef struct s_fpga_spice_opts t_fpga_spice_opts;

13
vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_api.c
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@ -28,6 +28,7 @@
#include "fpga_spice_backannotate_utils.h"
#include "fpga_spice_globals.h"
#include "fpga_spice_bitstream.h"
#include "verilog_modelsim_autodeck.h"
/* Include SynVerilog headers */
#include "verilog_global.h"
@ -38,11 +39,6 @@
#include "verilog_routing.h"
#include "verilog_top_netlist.h"
/* Global Variants available only in this source file */
static char* default_verilog_dir_name = "syn_verilogs/";
static char* default_lb_dir_name = "lb/";
static char* default_rr_dir_name = "routing/";
static char* default_submodule_dir_name = "sub_module/";
/***** Subroutines *****/
/* Alloc array that records Configuration bits for :
@ -251,6 +247,13 @@ void vpr_dump_syn_verilog(t_vpr_setup vpr_setup,
dump_fpga_spice_bitstream(bitstream_file_path, chomped_circuit_name, sram_verilog_orgz_info);
}
/* Output Modelsim Autodeck scripts */
if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_modelsim_autodeck) {
dump_verilog_modelsim_autodeck(sram_verilog_orgz_info, *(Arch.spice), num_clocks,
verilog_dir_formatted, chomped_circuit_name,
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.modelsim_ini_path);
}
/* dump verilog testbench only for input blif */
if ( TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_input_blif_tb) {
dump_verilog_input_blif_testbench(chomped_circuit_name, blif_testbench_file_path, num_clocks,

13
vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_global.c
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@ -13,10 +13,23 @@ float verilog_sim_timescale = 1e-9; // Verilog Simulation time scale (minimum ti
char* verilog_timing_preproc_flag = "ENABLE_TIMING"; // the flag to enable timing definition during compilation
char* verilog_init_sim_preproc_flag = "INITIALIZATION"; // the flag to enable initialization during simulation
char* default_verilog_dir_name = "syn_verilogs/";
char* default_lb_dir_name = "lb/";
char* default_rr_dir_name = "routing/";
char* default_submodule_dir_name = "sub_module/";
char* default_modelsim_dir_name = "msim_projects/";
char* modelsim_project_name_postfix = "_fpga_msim";
char* modelsim_proc_script_name_postfix = "_proc.tcl";
char* modelsim_top_script_name_postfix = "_runsim.tcl";
char* modelsim_testbench_module_postfix = "_top_tb";
char* modelsim_simulation_time_unit = "ms";
char* verilog_top_postfix = "_top.v";
char* bitstream_verilog_file_postfix = ".bitstream";
char* top_testbench_verilog_file_postfix = "_top_tb.v";
char* blif_testbench_verilog_file_postfix = "_blif_tb.v";
char* submodule_verilog_file_name = "sub_module.v";
char* logic_block_verilog_file_name = "logic_blocks.v";
char* luts_verilog_file_name = "luts.v";
char* routing_verilog_file_name = "routing.v";

13
vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_global.h
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@ -5,10 +5,23 @@ extern float verilog_sim_timescale;
extern char* verilog_timing_preproc_flag; // the flag to enable timing definition during compilation
extern char* verilog_init_sim_preproc_flag; // the flag to enable initialization during simulation
extern char* default_verilog_dir_name;
extern char* default_lb_dir_name;
extern char* default_rr_dir_name;
extern char* default_submodule_dir_name;
extern char* default_modelsim_dir_name;
extern char* modelsim_project_name_postfix;
extern char* modelsim_proc_script_name_postfix;
extern char* modelsim_top_script_name_postfix;
extern char* modelsim_testbench_module_postfix;
extern char* modelsim_simulation_time_unit;
extern char* verilog_top_postfix;
extern char* bitstream_verilog_file_postfix;
extern char* top_testbench_verilog_file_postfix;
extern char* blif_testbench_verilog_file_postfix;
extern char* submodule_verilog_file_name;
extern char* logic_block_verilog_file_name;
extern char* luts_verilog_file_name;
extern char* routing_verilog_file_name;

2
vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_submodules.c
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@ -2396,7 +2396,7 @@ void dump_verilog_submodules(char* submodule_dir,
vpr_printf(TIO_MESSAGE_INFO,"Generating header file for basic submodules...\n");
dump_verilog_subckt_header_file(submodule_verilog_subckt_file_path_head,
submodule_dir,
sub_module_verilog_file_name);
submodule_verilog_file_name);
return;
}