riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Correction pre-merge

This commit is contained in:
Baudouin Chauviere 2019-06-27 14:33:06 -06:00
parent 7c742f1cbb 8edd85c9fc
commit 04eb6d3488
9 changed files with 358 additions and 133 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp
View File

@ -505,6 +505,7 @@ t_track2track_map build_gsb_track_to_track_map(const t_rr_graph* rr_graph,
}
/* check if this track will start from here */
enum e_track_status track_status = determine_track_status_of_gsb(rr_gsb, gsb_side, inode);
switch (track_status) {
case TRACK_START:
/* update starting track list */

55
vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp
View File

@ -2124,32 +2124,41 @@ bool RRGSB::is_sb_node_mirror(const RRGSB& cand,
if (is_short_conkt != cand.is_sb_node_passing_wire(node_side, track_id)) {
return false;
} else { /* check driving rr_nodes */
if ( node->num_drive_rr_nodes != cand_node->num_drive_rr_nodes ) {
}
if (true == is_short_conkt) {
/* Since, both are pass wires,
* The two node should be equivalent
* we can return here
*/
return true;
}
/* For non-passing wires, check driving rr_nodes */
if ( node->num_drive_rr_nodes != cand_node->num_drive_rr_nodes ) {
return false;
}
for (size_t inode = 0; inode < size_t(node->num_drive_rr_nodes); ++inode) {
/* node type should be the same */
if ( node->drive_rr_nodes[inode]->type
!= cand_node->drive_rr_nodes[inode]->type) {
return false;
}
for (size_t inode = 0; inode < size_t(node->num_drive_rr_nodes); ++inode) {
/* node type should be the same */
if ( node->drive_rr_nodes[inode]->type
!= cand_node->drive_rr_nodes[inode]->type) {
return false;
}
/* switch type should be the same */
if ( node->drive_switches[inode]
!= cand_node->drive_switches[inode]) {
return false;
}
int src_node_id, des_node_id;
enum e_side src_node_side, des_node_side;
this->get_node_side_and_index(node->drive_rr_nodes[inode], OUT_PORT, &src_node_side, &src_node_id);
cand.get_node_side_and_index(cand_node->drive_rr_nodes[inode], OUT_PORT, &des_node_side, &des_node_id);
if (src_node_id != des_node_id) {
return false;
}
if (src_node_side != des_node_side) {
return false;
}
/* switch type should be the same */
if ( node->drive_switches[inode]
!= cand_node->drive_switches[inode]) {
return false;
}
int src_node_id, des_node_id;
enum e_side src_node_side, des_node_side;
this->get_node_side_and_index(node->drive_rr_nodes[inode], OUT_PORT, &src_node_side, &src_node_id);
cand.get_node_side_and_index(cand_node->drive_rr_nodes[inode], OUT_PORT, &des_node_side, &des_node_id);
if (src_node_id != des_node_id) {
return false;
}
if (src_node_side != des_node_side) {
return false;
}
}
return true;

19
vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_routing.c
View File

@ -859,24 +859,21 @@ void fpga_spice_generate_bitstream_routing_resources(char* routing_bitstream_log
/* Connection Boxes */
if (TRUE == compact_routing_hierarchy) {
vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for Connection blocks - X direction ...\n");
/* X - channels [1...nx][0..ny]*/
for (int iy = 0; iy < (ny + 1); ++iy) {
for (int ix = 1; ix < (nx + 1); ++ix) {
DeviceCoordinator gsb_range = device_rr_gsb.get_gsb_range();
vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for Connection blocks ...\n");
for (size_t ix = 0; ix < gsb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < gsb_range.get_y(); ++iy) {
const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
/* X - channels [1...nx][0..ny]*/
if ((TRUE == is_cb_exist(CHANX, ix, iy))
&&(true == rr_gsb.is_cb_exist(CHANX))) {
fpga_spice_generate_bitstream_routing_connection_box_subckt(fp,
rr_gsb, CHANX,
cur_sram_orgz_info);
}
}
}
/* Y - channels [1...ny][0..nx]*/
vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for Connection blocks - Y direction ...\n");
for (int ix = 0; ix < (nx + 1); ++ix) {
for (int iy = 1; iy < (ny + 1); ++iy) {
const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
/* Y - channels [1...ny][0..nx]*/
if ((TRUE == is_cb_exist(CHANY, ix, iy))
&&(true == rr_gsb.is_cb_exist(CHANY))) {
fpga_spice_generate_bitstream_routing_connection_box_subckt(fp,

8
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c
View File

@ -405,7 +405,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
t_pb_graph_node* prim_pb_graph_node,
int index,
t_spice_model* verilog_model) {
int i, ipin;
int i;
int lut_size = 0;
int num_input_port = 0;
t_spice_model_port** input_ports = NULL;
@ -418,12 +418,6 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
int num_mode_sram = 0;
t_spice_model_port* lut_sram_port = NULL;
int num_pb_type_input_port = 0;
t_port** pb_type_input_ports = NULL;
int num_pb_type_output_port = 0;
t_port** pb_type_output_ports = NULL;
char* formatted_subckt_prefix = format_verilog_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/
t_pb_type* cur_pb_type = NULL;
char* port_prefix = NULL;

215
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c
View File

@ -10,6 +10,7 @@
#include <assert.h>
#include <sys/stat.h>
#include <unistd.h>
#include <vector>
/* Include vpr structs*/
#include "util.h"
@ -22,6 +23,8 @@
#include "route_common.h"
#include "vpr_utils.h"
#include "rr_graph_builder_utils.h"
/* Include SPICE support headers*/
#include "linkedlist.h"
#include "rr_blocks.h"
@ -509,6 +512,52 @@ void verilog_generate_one_report_timing_sb_to_sb(FILE* fp,
return;
}
static
std::vector<t_rr_node*> build_ending_rr_node_for_one_sb_wire(t_rr_node* wire_rr_node,
t_rr_node* LL_rr_node) {
/* Initialization */
std::vector<t_rr_node*> end_rr_nodes;
end_rr_nodes.clear();
/* Get the cooridinator of the destination SB */
DeviceCoordinator end_sb_coordinator = get_chan_node_ending_sb_coordinator(wire_rr_node);
/* Get the sb */
const RRGSB& rr_sb = device_rr_gsb.get_gsb(end_sb_coordinator);
for (int iedge = 0; iedge < wire_rr_node->num_edges; iedge++) {
int inode = wire_rr_node->edges[iedge];
/* Double check if end_rr_node is in the GSB, we add it to the vector */
enum e_side side;
int index;
/* Build a list of ending rr_node we care */
/* Find the SB/CB block that it belongs to */
switch (LL_rr_node[inode].type) {
case IPIN:
rr_sb.get_node_side_and_index(&LL_rr_node[inode], IN_PORT, &side, &index);
if ( (OPEN != index) && (side != NUM_SIDES) ) {
end_rr_nodes.push_back(&LL_rr_node[inode]);
}
break;
case CHANX:
case CHANY:
rr_sb.get_node_side_and_index(&LL_rr_node[inode], OUT_PORT, &side, &index);
if ( (OPEN != index) && (side != NUM_SIDES) ) {
end_rr_nodes.push_back(&LL_rr_node[inode]);
}
break;
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid type of ending point rr_node!\n",
__FILE__, __LINE__);
exit(1);
}
}
return end_rr_nodes;
}
static
void build_ending_rr_node_for_one_sb_wire(t_rr_node* wire_rr_node,
t_rr_node* LL_rr_node,
@ -612,9 +661,9 @@ void build_ending_rr_node_for_one_sb_wire(t_rr_node* wire_rr_node,
*/
static
void verilog_generate_report_timing_one_sb_thru_segments(FILE* fp,
RRGSB src_sb,
const RRGSB& src_sb,
t_rr_node* src_rr_node,
RRGSB des_sb,
const RRGSB& des_sb,
t_rr_node* des_rr_node,
char* rpt_name) {
/* Check the file handler */
@ -710,9 +759,6 @@ void verilog_generate_report_timing_one_sb_ending_segments(FILE* fp,
t_rr_node* src_rr_node,
t_rr_node* des_rr_node,
char* rpt_name) {
t_cb* next_cb = NULL;
DeviceCoordinator next_sb_coordinator;
RRGSB next_sb;
/* Check the file handler */
if (NULL == fp) {
@ -723,20 +769,22 @@ void verilog_generate_report_timing_one_sb_ending_segments(FILE* fp,
}
switch (des_rr_node->type) {
case IPIN:
case IPIN: {
/* Get the coordinate of ending CB */
next_cb = get_chan_rr_node_ending_cb(src_rr_node, des_rr_node);
t_cb* next_cb = get_chan_rr_node_ending_cb(src_rr_node, des_rr_node);
verilog_generate_one_report_timing_sb_to_cb(fp, src_sb, src_rr_node,
next_cb, des_rr_node);
break;
}
case CHANX:
case CHANY:
case CHANY: {
/* Get the coordinate of ending SB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
DeviceCoordinator next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
const RRGSB& next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
verilog_generate_one_report_timing_sb_to_sb(fp, src_sb, src_rr_node,
next_sb, src_rr_node);
break;
}
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid type of ending point rr_node!\n",
__FILE__, __LINE__);
@ -827,7 +875,6 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
t_cb* next_cb = NULL;
char* rpt_name = NULL;
DeviceCoordinator next_sb_coordinator;
RRGSB next_sb;
/* Check the file handler */
if (NULL == fp) {
@ -957,13 +1004,14 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
* ---------
*/
case CHANX:
case CHANY:
case CHANY: {
/* Get the coordinate of ending CB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
const RRGSB& next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
end_sb_x = next_sb.get_sb_x();
end_sb_y = next_sb.get_sb_y();
break;
}
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid type of rr_node!\n",
__FILE__, __LINE__);
@ -999,24 +1047,26 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
fprintf(fp, " -unconstrained");
break;
case CHANX:
case CHANY:
/* Get the coordinate of ending SB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
case CHANY: {
/* Get the coordinate of ending SB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
const RRGSB& next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
fprintf(fp, " -to ");
/* output instance name */
fprintf(fp, "%s/",
next_sb.gen_sb_verilog_instance_name());
/* Find which side the ending pin locates, and determine the coordinate */
dump_verilog_one_sb_chan_pin(fp, next_sb, src_rr_node, IN_PORT);
fprintf(fp, " -point_to_point");
fprintf(fp, " -unconstrained");
break;
/* All the types are verified before */
fprintf(fp, " -to ");
/* output instance name */
fprintf(fp, "%s/",
next_sb.gen_sb_verilog_instance_name());
/* Find which side the ending pin locates, and determine the coordinate */
dump_verilog_one_sb_chan_pin(fp, next_sb, src_rr_node, IN_PORT);
fprintf(fp, " -point_to_point");
fprintf(fp, " -unconstrained");
break;
}
/* Verification is done before the loops.*/
default:
break;
}
@ -1047,10 +1097,10 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
fprintf(fp, " -unconstrained");
break;
case CHANX:
case CHANY:
case CHANY: {
/* Get the coordinate of ending SB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
const RRGSB& next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
fprintf(fp, " -to ");
@ -1064,7 +1114,9 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
fprintf(fp, " -unconstrained");
break;
/* All the types are verified before */
}
/* Verification is done before the loops.*/
default:
break;
}
@ -1095,10 +1147,10 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
fprintf(fp, " -unconstrained");
break;
case CHANX:
case CHANY:
case CHANY: {
/* Get the coordinate of ending SB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
const RRGSB& next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
fprintf(fp, " -to ");
@ -1112,7 +1164,9 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
fprintf(fp, " -unconstrained");
break;
/* All the types are verified before */
}
/* Verification is done before the loops.*/
default:
break;
}
@ -1143,10 +1197,10 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
fprintf(fp, " -unconstrained");
break;
case CHANX:
case CHANY:
case CHANY: {
/* Get the coordinate of ending SB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
const RRGSB& next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
fprintf(fp, " -to ");
@ -1160,7 +1214,9 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
fprintf(fp, " -unconstrained");
break;
/* All the types are verified before */
}
/* Verification is done before the loops.*/
default:
break;
}
@ -1195,7 +1251,6 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
int path_cnt) {
int L_wire;
int ix, iy;
int cur_sb_x, cur_sb_y;
int end_sb_x, end_sb_y;
t_cb* next_cb = NULL;
t_sb* next_sb = NULL;
@ -1343,8 +1398,6 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
}
/* Get the base coordinate of src_sb */
cur_sb_x = src_sb_info->x;
cur_sb_y = src_sb_info->y;
/* 4 cases: */
if ((INC_DIRECTION == src_rr_node->direction)
&&(CHANX == src_rr_node->type)) {
@ -1378,6 +1431,10 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
fprintf(fp, " -point_to_point");
fprintf(fp, " -unconstrained");
break;
/* Verification is done before the loops.*/
default:
break;
}
@ -1415,6 +1472,10 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
fprintf(fp, " -point_to_point");
fprintf(fp, " -unconstrained");
break;
/* Verification is done before the loops.*/
default:
break;
}
@ -1452,6 +1513,10 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
fprintf(fp, " -point_to_point");
fprintf(fp, " -unconstrained");
break;
/* Verification is done before the loops.*/
default:
break;
}
@ -1489,6 +1554,10 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
fprintf(fp, " -point_to_point");
fprintf(fp, " -unconstrained");
break;
/* Verification is done before the loops.*/
default:
break;
}
@ -1520,7 +1589,6 @@ void dump_verilog_sb_through_routing_pins(FILE* fp,
size_t end_sb_x, end_sb_y;
t_cb* next_cb;
DeviceCoordinator next_sb_coordinator;
RRGSB next_sb;
/* Check the file handler */
if (NULL == fp) {
@ -1632,13 +1700,14 @@ void dump_verilog_sb_through_routing_pins(FILE* fp,
* ---------
*/
case CHANX:
case CHANY:
case CHANY: {
/* Get the coordinate of ending CB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
const RRGSB& next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
end_sb_x = next_sb.get_sb_x();
end_sb_y = next_sb.get_sb_y();
break;
}
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid type of rr_node!\n",
__FILE__, __LINE__);
@ -1657,7 +1726,7 @@ void dump_verilog_sb_through_routing_pins(FILE* fp,
fprintf(fp, " ");
/* output instance name */
DeviceCoordinator inter_sb_coordinator(ix, cur_sb_y);
RRGSB inter_sb = device_rr_gsb.get_gsb(inter_sb_coordinator);
const RRGSB& inter_sb = device_rr_gsb.get_gsb(inter_sb_coordinator);
fprintf(fp, "%s/",
inter_sb.gen_sb_verilog_instance_name());
dump_verilog_one_sb_chan_pin(fp, inter_sb, src_rr_node, IN_PORT);
@ -1676,7 +1745,7 @@ void dump_verilog_sb_through_routing_pins(FILE* fp,
fprintf(fp, " ");
/* output instance name */
DeviceCoordinator inter_sb_coordinator(cur_sb_x, iy);
RRGSB inter_sb = device_rr_gsb.get_gsb(inter_sb_coordinator);
const RRGSB& inter_sb = device_rr_gsb.get_gsb(inter_sb_coordinator);
fprintf(fp, "%s/",
inter_sb.gen_sb_verilog_instance_name());
dump_verilog_one_sb_chan_pin(fp, inter_sb, src_rr_node, IN_PORT);
@ -1695,7 +1764,7 @@ void dump_verilog_sb_through_routing_pins(FILE* fp,
fprintf(fp, " ");
/* output instance name */
DeviceCoordinator inter_sb_coordinator(ix, cur_sb_y);
RRGSB inter_sb = device_rr_gsb.get_gsb(inter_sb_coordinator);
const RRGSB& inter_sb = device_rr_gsb.get_gsb(inter_sb_coordinator);
fprintf(fp, "%s/",
inter_sb.gen_sb_verilog_instance_name());
dump_verilog_one_sb_chan_pin(fp, inter_sb, src_rr_node, IN_PORT);
@ -1714,7 +1783,7 @@ void dump_verilog_sb_through_routing_pins(FILE* fp,
fprintf(fp, " ");
/* output instance name */
DeviceCoordinator inter_sb_coordinator(cur_sb_x, iy);
RRGSB inter_sb = device_rr_gsb.get_gsb(inter_sb_coordinator);
const RRGSB& inter_sb = device_rr_gsb.get_gsb(inter_sb_coordinator);
fprintf(fp, "%s/",
inter_sb.gen_sb_verilog_instance_name());
dump_verilog_one_sb_chan_pin(fp, inter_sb, src_rr_node, IN_PORT);
@ -1970,7 +2039,6 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp,
assert( ( CHANX == wire_rr_node->type )
|| ( CHANY == wire_rr_node->type ));
int track_idx = wire_rr_node->ptc_num;
t_rr_type cb_type = wire_rr_node->type;
/* We only care a specific length of wires */
@ -1990,8 +2058,7 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp,
int inode = wire_rr_node->edges[jedge];
/* Find the SB/CB block that it belongs to */
switch (LL_rr_node[inode].type) {
case IPIN:
{
case IPIN: {
DeviceCoordinator next_cb_coordinator = get_chan_node_ending_cb(wire_rr_node, &(LL_rr_node[inode]));
/* Get the coordinate of ending CB */
const RRGSB& next_cb = device_rr_gsb.get_gsb(next_cb_coordinator);
@ -2017,9 +2084,21 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp,
/* output instance name */
fprintf(fp, "%s/",
next_cb.gen_cb_verilog_instance_name(cb_type));
/* FIXME: we should avoid using global variables !!!! */
/* If we have an mirror SB, we should the module name of the mirror !!! */
DeviceCoordinator coordinator = next_cb.get_sb_coordinator();
const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, coordinator);
enum e_side pin_gsb_side = next_cb.get_cb_chan_side(cb_type);
/* We get the index and side for the cur_rr_node in the mother rr_sb context */
int pin_node_id = next_cb.get_chan_node_index(pin_gsb_side, wire_rr_node);
/* Make sure we have valid numbers */
assert ( -1 != pin_node_id );
/* output pin name */
fprintf(fp, "%s",
next_cb.gen_cb_verilog_routing_track_name(cb_type, track_idx));
unique_mirror.gen_cb_verilog_routing_track_name(cb_type, pin_node_id));
/* Print through pins */
if (TRUE == sdc_opts.print_thru_pins) {
fprintf(fp, " -through_pins ");
@ -2029,11 +2108,10 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp,
}
fprintf(fp, " -unconstrained\n");
path_cnt++;
}
break;
}
case CHANX:
case CHANY:
{
case CHANY: {
DeviceCoordinator next_sb_coordinator;
/* Get the coordinate of ending SB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(wire_rr_node, &(LL_rr_node[inode]));
@ -2079,8 +2157,8 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp,
path_cnt++;
/* Set the flag */
sb_dumped = TRUE;
}
break;
}
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid type of ending point rr_node!\n",
__FILE__, __LINE__);
@ -2403,13 +2481,11 @@ static
void verilog_generate_one_routing_segmental_report_timing(FILE* fp,
t_syn_verilog_opts fpga_verilog_opts,
const RRGSB& rr_sb,
t_rr_node* wire_rr_node,
enum e_side gsb_side,
int wire_rr_node_id,
t_rr_node* LL_rr_node,
char* direction,
int* path_cnt) {
int num_end_rr_nodes = 0;
t_rr_node** end_rr_node = NULL;
/* Check the file handler */
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,
@ -2417,24 +2493,24 @@ void verilog_generate_one_routing_segmental_report_timing(FILE* fp,
__FILE__, __LINE__);
exit(1);
}
t_rr_node* wire_rr_node = rr_sb.get_chan_node(gsb_side, wire_rr_node_id);
assert( ( CHANX == wire_rr_node->type )
|| ( CHANY == wire_rr_node->type ));
/* Find the farest ending points!*/
build_ending_rr_node_for_one_sb_wire(wire_rr_node, LL_rr_node,
&num_end_rr_nodes, &end_rr_node);
std::vector<t_rr_node*> end_rr_nodes = build_ending_rr_node_for_one_sb_wire(wire_rr_node, LL_rr_node);
/* Find the starting points */
for (int iedge = 0; iedge < wire_rr_node->num_drive_rr_nodes; iedge++) {
/* Find the ending points*/
for (int jedge = 0; jedge < num_end_rr_nodes; jedge++) {
for (size_t jedge = 0; jedge < end_rr_nodes.size(); jedge++) {
/* Report timing */
dump_verilog_one_sb_wire_segemental_report_timing(fp, fpga_verilog_opts,
rr_sb,
wire_rr_node->drive_rr_nodes[iedge],
wire_rr_node,
end_rr_node[jedge],
end_rr_nodes[jedge],
direction,
*path_cnt);
/* Update counter */
@ -2442,9 +2518,6 @@ void verilog_generate_one_routing_segmental_report_timing(FILE* fp,
}
}
/* Free */
my_free(end_rr_node);
return;
}
@ -2670,7 +2743,7 @@ void verilog_generate_routing_wire_report_timing(t_trpt_opts trpt_opts,
DeviceCoordinator sb_range = device_rr_gsb.get_gsb_range();
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
RRGSB rr_sb = device_rr_gsb.get_gsb(ix, iy);
const RRGSB& rr_sb = device_rr_gsb.get_gsb(ix, iy);
for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) {
Side side_manager(side);
for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) {
@ -2705,7 +2778,7 @@ void verilog_generate_routing_wire_report_timing(t_trpt_opts trpt_opts,
/* Dump report_timing command */
verilog_generate_one_routing_segmental_report_timing(fp, fpga_verilog_opts,
rr_sb,
rr_sb.get_chan_node(side_manager.get_side(), itrack),
side_manager.get_side(), itrack,
LL_rr_node, "horizontal", &path_cnt);
/* Disable the timing again */
/*fprintf(fp, "# Set disable timing for the following Switch Block output:\n");

21
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
View File

@ -492,7 +492,7 @@ void dump_verilog_unique_switch_box_chan_port(FILE* fp,
convert_chan_type_to_string(chan_rr_node_type),
chan_rr_node_coordinator.get_x(), chan_rr_node_coordinator.get_y(),
convert_chan_rr_node_direction_to_string(cur_rr_node_direction),
cur_rr_node->ptc_num);
index); /* use node index since ptc_num is no longer unique */
return;
}
@ -529,7 +529,7 @@ void dump_verilog_unique_switch_box_short_interc(FILE* fp,
char* des_chan_port_name = "out";
fprintf(fp, "//----- Short connection %s[%lu][%lu]_%s[%d] -----\n",
chan_name, rr_sb.get_sb_coordinator().get_x(), rr_sb.get_sb_coordinator().get_y(), des_chan_port_name, cur_rr_node->ptc_num);
chan_name, rr_sb.get_sb_coordinator().get_x(), rr_sb.get_sb_coordinator().get_y(), des_chan_port_name, index);
fprintf(fp, "assign ");
/* Output port */
@ -3916,8 +3916,6 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
if (TRUE == compact_routing_hierarchy) {
/* Create a snapshot on sram_orgz_info */
t_sram_orgz_info* stamped_sram_orgz_info = snapshot_sram_orgz_info(cur_sram_orgz_info);
/* Restore sram_orgz_info to the base */
copy_sram_orgz_info (cur_sram_orgz_info, stamped_sram_orgz_info);
DeviceCoordinator cb_range = device_rr_gsb.get_gsb_range();
@ -3928,14 +3926,6 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
verilog_dir, subckt_dir, unique_mirror, CHANX,
FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog);
}
/* TODO: when we follow a tile organization,
* updating the conf bits should follow a tile organization: CLB, SB and CBX, CBY */
for (size_t ix = 0; ix < cb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < cb_range.get_y(); ++iy) {
const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
update_routing_connection_box_conf_bits(cur_sram_orgz_info, rr_gsb, CHANX);
}
}
/* Y - channels [1...ny][0..nx]*/
for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) {
@ -3945,12 +3935,19 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog);
}
/* Restore sram_orgz_info to the base */
copy_sram_orgz_info (cur_sram_orgz_info, stamped_sram_orgz_info);
/* TODO: when we follow a tile organization,
* updating the conf bits should follow a tile organization: CLB, SB and CBX, CBY */
for (size_t ix = 0; ix < cb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < cb_range.get_y(); ++iy) {
const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
update_routing_connection_box_conf_bits(cur_sram_orgz_info, rr_gsb, CHANX);
update_routing_connection_box_conf_bits(cur_sram_orgz_info, rr_gsb, CHANY);
}
}
/* Free */
free_sram_orgz_info(stamped_sram_orgz_info, stamped_sram_orgz_info->type);
} else {

38
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c
View File

@ -678,19 +678,49 @@ void verilog_generate_sdc_constrain_one_cb_path(FILE* fp,
fprintf(fp, " -from ");
fprintf(fp, "%s/",
rr_gsb.gen_cb_verilog_instance_name(cb_type));
/* FIXME: we should avoid using global variables !!!! */
/* If we have an mirror SB, we should the module name of the mirror !!! */
DeviceCoordinator coordinator = rr_gsb.get_sb_coordinator();
const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, coordinator);
enum e_side chan_gsb_side = rr_gsb.get_cb_chan_side(cb_type);
/* We get the index and side for the cur_rr_node in the mother rr_sb context */
int chan_node_id = rr_gsb.get_chan_node_index(chan_gsb_side, src_rr_node);
/* Make sure we have valid numbers */
assert ( -1 != chan_node_id );
fprintf(fp, "%s",
rr_gsb.gen_cb_verilog_routing_track_name(cb_type, src_rr_node->ptc_num));
unique_mirror.gen_cb_verilog_routing_track_name(cb_type, chan_node_id));
fprintf(fp, " -to ");
fprintf(fp, "%s/",
rr_gsb.gen_cb_verilog_instance_name(cb_type));
std::vector<enum e_side> ipin_gsb_sides = rr_gsb.get_cb_ipin_sides(cb_type);
enum e_side ipin_gsb_side = NUM_SIDES;
int ipin_node_id = -1;
for (size_t side_id = 0; side_id < ipin_gsb_sides.size(); ++side_id) {
/* Try to get a node_index, port direction does not matter for IPINs node */
ipin_node_id = rr_gsb.get_node_index(des_rr_node, ipin_gsb_sides[side_id], OUT_PORT);
if (-1 != ipin_node_id) {
/* We find a valid side ! Exit the for loop then */
ipin_gsb_side = ipin_gsb_sides[side_id];
break;
}
}
/* Make sure we have valid numbers */
assert ( ( NUM_SIDES != ipin_gsb_side ) && ( -1 != ipin_node_id ) );
/* Get the mirror node in unique_module */
t_rr_node* mirror_ipin_node = unique_mirror.get_ipin_node(ipin_gsb_side, ipin_node_id);
/* Make sure grid_side matches between mirror_node and des_rr_node */
assert ( des_rr_node_grid_side == unique_mirror.get_ipin_node_grid_side(ipin_gsb_side, ipin_node_id));
dump_verilog_grid_side_pin_with_given_index(fp, IPIN, /* This is an output of a connection box */
des_rr_node->ptc_num,
mirror_ipin_node->ptc_num,
des_rr_node_grid_side,
des_rr_node->xlow,
des_rr_node->ylow,
mirror_ipin_node->xlow,
mirror_ipin_node->ylow,
FALSE);
/* If src_node == des_node, this is a metal wire */

132
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c
View File

@ -22,6 +22,8 @@
#include "route_common.h"
#include "vpr_utils.h"
#include "rr_graph_builder_utils.h"
/* Include SPICE support headers*/
#include "linkedlist.h"
#include "fpga_x2p_types.h"
@ -82,7 +84,13 @@ void dump_verilog_one_sb_chan_pin(FILE* fp,
/* Get the coordinate of chanx or chany*/
/* Find the coordinate of the cur_rr_node */
rr_sb.get_node_side_and_index(cur_rr_node, port_type, &side, &track_idx);
DeviceCoordinator chan_coordinator = rr_sb.get_side_block_coordinator(side);
/* FIXME: we should avoid using global variables !!!! */
/* If we have an mirror SB, we should the module name of the mirror !!! */
DeviceCoordinator coordinator = rr_sb.get_sb_coordinator();
const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(coordinator);
DeviceCoordinator chan_coordinator = unique_mirror.get_side_block_coordinator(side);
/* Print the pin of the cur_rr_node */
pin_name = gen_verilog_routing_channel_one_pin_name(cur_rr_node,
chan_coordinator.get_x(),
@ -151,17 +159,36 @@ void dump_verilog_one_sb_routing_pin(FILE* fp,
/* Get the top-level pin name and print it out */
/* Depends on the type of node */
switch (cur_rr_node->type) {
case OPIN:
case OPIN: {
/* Identify the side of OPIN on a grid */
side = get_grid_pin_side(cur_rr_node->xlow, cur_rr_node->ylow, cur_rr_node->ptc_num);
assert (OPEN != side);
/* FIXME: we should avoid using global variables !!!! */
/* If we have an mirror SB, we should the module name of the mirror !!! */
DeviceCoordinator coordinator = rr_sb.get_sb_coordinator();
const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(coordinator);
enum e_side pin_gsb_side = NUM_SIDES;
int pin_node_id = -1;
/* We get the index and side for the cur_rr_node in the mother rr_sb context */
rr_sb.get_node_side_and_index(cur_rr_node, IN_PORT, &pin_gsb_side, &pin_node_id);
/* Make sure we have valid numbers */
assert ( (NUM_SIDES != pin_gsb_side) && (-1 != pin_node_id) );
/* We get rr_node with the same index and side in the unique mirror context */
t_rr_node* mirror_node = unique_mirror.get_opin_node(pin_gsb_side, pin_node_id);
/* Identify the side of OPIN on a grid */
side = get_grid_pin_side(mirror_node->xlow, mirror_node->ylow, mirror_node->ptc_num);
assert (OPEN != side);
dump_verilog_grid_side_pin_with_given_index(fp, OPIN,
cur_rr_node->ptc_num,
mirror_node->ptc_num,
side,
cur_rr_node->xlow,
cur_rr_node->ylow,
mirror_node->xlow,
mirror_node->ylow,
FALSE); /* Do not specify direction of port */
break;
}
case CHANX:
case CHANY:
dump_verilog_one_sb_chan_pin(fp, rr_sb, cur_rr_node, IN_PORT);
@ -363,6 +390,100 @@ t_cb* get_chan_rr_node_ending_cb(t_rr_node* src_rr_node,
return next_cb;
}
/** Given a starting rr_node (CHANX or CHANY)
* return the sb contains both (the ending CB of the routing wire)
*/
DeviceCoordinator get_chan_node_ending_sb_coordinator(t_rr_node* src_rr_node) {
/* Get the coordinator where the node ends */
DeviceCoordinator end_coordinator = get_track_rr_node_end_coordinator(src_rr_node);
/* Initilizae the SB coordinator where the node ends */
DeviceCoordinator sb_coordinator;
/* Case 1:
* end_rr_node(chany[x][y+1])
* /|\
* |
* ---------
* | |
* src_rr_node ------>| next_sb |-------> end_rr_node
* (chanx[x][y]) | [x][y] | (chanx[x+1][y]
* ---------
* |
* \|/
* end_rr_node(chany[x][y])
*/
if ( (CHANX == src_rr_node->type)
&& (INC_DIRECTION == src_rr_node->direction) ) {
/* SB coordinator is the same as src rr_node */
sb_coordinator.set(end_coordinator.get_x(), end_coordinator.get_y());
}
/* Case 2
* end_rr_node(chany[x][y+1])
* /|\
* |
* ---------
* | |
* end_rr_node <------| next_sb |<-------- src_rr_node
* (chanx[x][y]) | [x][y] | (chanx[x+1][y]
* ---------
* |
* \|/
* end_rr_node(chany[x][y])
*/
if ( (CHANX == src_rr_node->type)
&& (DEC_DIRECTION == src_rr_node->direction) ) {
/* SB coordinator is the [x-1][y] */
sb_coordinator.set(end_coordinator.get_x() - 1, end_coordinator.get_y());
}
/* Case 3
* end_rr_node(chany[x][y+1])
* /|\
* |
* ---------
* | |
* end_rr_node <------| next_sb |-------> src_rr_node
* (chanx[x][y]) | [x][y] | (chanx[x+1][y]
* ---------
* /|\
* |
* src_rr_node(chany[x][y])
*/
if ( (CHANY == src_rr_node->type)
&& (INC_DIRECTION == src_rr_node->direction) ) {
/* SB coordinator is the same */
sb_coordinator.set(end_coordinator.get_x(), end_coordinator.get_y());
}
/* Case 4
* src_rr_node(chany[x][y+1])
* |
* \|/
* ---------
* | |
* end_rr_node <------| next_sb |--------> end_rr_node
* (chanx[x][y]) | [x][y] | (chanx[x+1][y]
* ---------
* |
* \|/
* end_rr_node(chany[x][y])
*/
if ( (CHANY == src_rr_node->type)
&& (DEC_DIRECTION == src_rr_node->direction) ) {
/* SB coordinator is the [x][y-1] */
sb_coordinator.set(end_coordinator.get_x(), end_coordinator.get_y() - 1);
}
const RRGSB& rr_sb = device_rr_gsb.get_gsb(sb_coordinator);
/* Double check if src_rr_node is in the list */
enum e_side side;
int index;
rr_sb.get_node_side_and_index(src_rr_node, IN_PORT, &side, &index);
assert ( (OPEN != index) && (side != NUM_SIDES) );
/* Passing the check, assign coordinator of next_sb */
return sb_coordinator;
}
/** Given a starting rr_node (CHANX or CHANY)
* and a ending rr_node (IPIN)
* return the sb contains both (the ending CB of the routing wire)
@ -689,6 +810,7 @@ void set_disable_timing_one_sb_output(FILE* fp,
/* output instance name */
fprintf(fp, "%s/",
rr_sb.gen_sb_verilog_instance_name());
dump_verilog_one_sb_chan_pin(fp, rr_sb, wire_rr_node, OUT_PORT);
fprintf(fp, "\n");

2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.h
View File

@ -32,6 +32,8 @@ DeviceCoordinator get_chan_node_ending_cb(t_rr_node* src_rr_node,
t_cb* get_chan_rr_node_ending_cb(t_rr_node* src_rr_node,
t_rr_node* end_rr_node);
DeviceCoordinator get_chan_node_ending_sb_coordinator(t_rr_node* src_rr_node);
DeviceCoordinator get_chan_node_ending_sb_coordinator(t_rr_node* src_rr_node,
t_rr_node* end_rr_node);