Update spice path in architecture
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@ -330,7 +330,7 @@
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<port type="output" prefix="out" size="1"/>
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</spice_model>
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<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
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<spice_model type="ff" name="static_dff" prefix="dff" spice_netlist="SpiceNetlists/ff.sp" verilog_netlist="/home/travis/build/LNIS-Projects/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/ff.v">
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<spice_model type="ff" name="static_dff" prefix="dff" spice_netlist="/home/travis/build/LNIS-Projects/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="/home/travis/build/LNIS-Projects/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/ff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="on" spice_model_name="INV1X"/>
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<output_buffer exist="on" spice_model_name="INV1X"/>
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@ -372,7 +372,7 @@
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<port type="sram" prefix="mode" size="2" mode_select="true" spice_model_name="sc_dff_compact" default_val="1"/>
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</spice_model>
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<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
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<spice_model type="sff" name="sc_dff_compact" prefix="scff" spice_netlist="SpiceNetlists/ff.sp" verilog_netlist="/home/travis/build/LNIS-Projects/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/ff.v">
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<spice_model type="sff" name="sc_dff_compact" prefix="scff" spice_netlist="/home/travis/build/LNIS-Projects/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="/home/travis/build/LNIS-Projects/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/ff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="on" spice_model_name="INV1X"/>
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<output_buffer exist="on" spice_model_name="INV1X"/>
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@ -384,7 +384,7 @@
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<port type="output" prefix="Qb" size="1"/>
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<port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
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</spice_model>
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<spice_model type="iopad" name="iopad" prefix="iopad" spice_netlist="SpiceNetlists/io.sp" verilog_netlist="/home/travis/build/LNIS-Projects/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/io.v">
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<spice_model type="iopad" name="iopad" prefix="iopad" spice_netlist="/home/travis/build/LNIS-Projects/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/io.sp" verilog_netlist="/home/travis/build/LNIS-Projects/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/io.v">
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<design_technology type="cmos"/>
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<input_buffer exist="on" spice_model_name="INV1X"/>
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<output_buffer exist="on" spice_model_name="INV1X"/>
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@ -397,7 +397,7 @@
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<port type="output" prefix="inpad" size="1"/>
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</spice_model>
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<!-- Hard logic definition for heterogenous blocks -->
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<spice_model type="hard_logic" name="adder" prefix="adder" dump_explicit_port_map="true" spice_netlist="SpiceNetlists/adder.sp" verilog_netlist="/home/travis/build/LNIS-Projects/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/adder.v">
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<spice_model type="hard_logic" name="adder" prefix="adder" dump_explicit_port_map="true" spice_netlist="/home/travis/build/LNIS-Projects/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/adder.sp" verilog_netlist="/home/travis/build/LNIS-Projects/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/adder.v">
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<design_technology type="cmos"/>
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<input_buffer exist="on" spice_model_name="INV1X"/>
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<output_buffer exist="on" spice_model_name="INV1X"/>
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@ -407,7 +407,7 @@
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<port type="output" prefix="sumout" size="1"/>
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<port type="output" prefix="cout" size="1"/>
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</spice_model>
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<spice_model type="sram" name="sram6T" prefix="sram" spice_netlist="SpiceNetlists/sram.sp" verilog_netlist="/home/travis/build/LNIS-Projects/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/sram.v">
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<spice_model type="sram" name="sram6T" prefix="sram" spice_netlist="/home/travis/build/LNIS-Projects/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="/home/travis/build/LNIS-Projects/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/sram.v">
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<design_technology type="cmos"/>
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<input_buffer exist="on" spice_model_name="INV1X"/>
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<output_buffer exist="on" spice_model_name="INV1X"/>
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