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Fix sdc analysis bug related to virtual nodes + add the option in regression test

This commit is contained in:
AurelienUoU 2019-06-05 12:10:28 -06:00
parent d24488092d
commit 84fabbd43b
3 changed files with 9 additions and 5 deletions
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1
vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_pb_rr_graph.c
View File

@ -1274,6 +1274,7 @@ int add_virtual_sources_to_rr_graph_multi_sources(t_rr_graph* local_rr_graph) {
local_rr_graph->rr_node[unique_src_node].fan_in = 0;
local_rr_graph->rr_node[unique_src_node].num_drive_rr_nodes = 0;
local_rr_graph->rr_node[unique_src_node].drive_rr_nodes = NULL;
local_rr_graph->rr_node[unique_src_node].pb_graph_pin = NULL;
local_rr_graph->rr_node[unique_src_node].num_edges = local_rr_graph->net_num_sources[inet];
local_rr_graph->rr_node[unique_src_node].edges = (int*) my_calloc(local_rr_graph->rr_node[unique_src_node].num_edges, sizeof(int));
local_rr_graph->rr_node[unique_src_node].switches = (short*) my_calloc(local_rr_graph->rr_node[unique_src_node].num_edges, sizeof(short));

11
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c
View File

@ -772,7 +772,7 @@ void verilog_generate_sdc_disable_one_unused_chan(FILE* fp,
fprintf(fp,
"##################################################\n");
fprintf(fp,
"### Disable Timing for an flag 1 %s[%d][%d] ###\n",
"### Disable Timing for an %s[%d][%d] ###\n",
convert_chan_type_to_string(rr_chan.get_type()),
x, y);
fprintf(fp,
@ -833,7 +833,7 @@ void verilog_generate_sdc_disable_one_unused_chan(FILE* fp,
fprintf(fp,
"##################################################\n");
fprintf(fp,
"### Disable Timing for an flag 2 %s[%d][%d] ###\n",
"### Disable Timing for an %s[%d][%d] ###\n",
convert_chan_type_to_string(chan_type),
x, y);
fprintf(fp,
@ -1592,10 +1592,13 @@ void verilog_generate_sdc_disable_one_unused_block(FILE* fp,
for (inode = 0; inode < cur_phy_pb->rr_graph->num_rr_nodes; inode++) {
/* Focus on the SOURCE and SINK rr_nodes */
if ((SOURCE != cur_phy_pb->rr_graph->rr_node[inode].type)
&& (SINK != cur_phy_pb->rr_graph->rr_node[inode].type)
&& (NULL == cur_phy_pb->rr_graph->rr_node[inode].pb_graph_pin)) {
&& (SINK != cur_phy_pb->rr_graph->rr_node[inode].type)) {
continue;
}
/* Check if pin is virtual */
if (NULL == cur_phy_pb->rr_graph->rr_node[inode].pb_graph_pin) {
continue;
}
/* Identify if the rr_node is usused */
if (FALSE == is_rr_node_to_be_disable_for_analysis(&(cur_phy_pb->rr_graph->rr_node[inode]))) {
continue;

2
vpr7_x2p/vpr/regression_verilog.sh
View File

@ -23,7 +23,7 @@ rm -rf $verilog_output_dirpath/$verilog_output_dirname
# Run VPR
#valgrind
./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties OPENFPGAPATHKEYWORD/fpga_flow/tech/PTM_45nm/45nm.xml --fpga_verilog_print_sdc_pnr #--fpga_verilog_print_sdc_analysis
./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties OPENFPGAPATHKEYWORD/fpga_flow/tech/PTM_45nm/45nm.xml --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis