Bug fix in cpp
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332ce17f03
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@ -852,14 +852,13 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
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fprintf(fp, "# L%d wire, Path ID: %d\n",
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L_wire,
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path_cnt);
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fprintf(fp, "report_timing -from ");
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/* output instance name */
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fprintf(fp, "%s/",
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src_sb.gen_sb_verilog_instance_name());
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/* Find which side the ending pin locates, and determine the coordinate */
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dump_verilog_one_sb_routing_pin(fp, src_sb, src_rr_node);
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dump_verilog_one_sb_routing_pin(fp, src_sb, drive_rr_node);
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/* Switch depends on the type of des_rr_node */
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switch(des_rr_node->type) {
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@ -1000,6 +999,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
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break;
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case CHANX:
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case CHANY:
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verilog_generate_report_timing_one_sb_ending_segments
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/* Get the coordinate of ending SB */
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next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
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next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
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@ -1015,6 +1015,8 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
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fprintf(fp, " -point_to_point");
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fprintf(fp, " -unconstrained");
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break;
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default:
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break;
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}
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}
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@ -3044,11 +3046,8 @@ void verilog_generate_routing_report_timing(t_trpt_opts trpt_opts,
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fp = wireL_cnt->file_handler;
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/* This is a new L-wire, create the file handler and the mkdir command to the TCL script */
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if (0 == path_cnt) {
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fprintf(fp, "if {![file exists $%s]} {\n",
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gen_verilog_one_routing_report_timing_Lwire_dir_path(fpga_verilog_opts.report_timing_path, L_wire));
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fprintf(fp, "exec mkdir -p %s\n",
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gen_verilog_one_routing_report_timing_Lwire_dir_path(fpga_verilog_opts.report_timing_path, L_wire));
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fprintf(fp, "}\n");
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}
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/* Restore the disable_timing for the SB outputs on the path */
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/*fprintf(fp, "# Restore disable timing for the following Switch Block output:\n");
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@ -3112,11 +3111,8 @@ void verilog_generate_routing_report_timing(t_trpt_opts trpt_opts,
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fp = wireL_cnt->file_handler;
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/* This is a new L-wire, create the file handler and the mkdir command to the TCL script */
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if (0 == path_cnt) {
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fprintf(fp, "if {![file exists $%s]} {\n",
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gen_verilog_one_routing_report_timing_Lwire_dir_path(fpga_verilog_opts.report_timing_path, L_wire));
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fprintf(fp, "exec mkdir -p %s\n",
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gen_verilog_one_routing_report_timing_Lwire_dir_path(fpga_verilog_opts.report_timing_path, L_wire));
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fprintf(fp, "}\n");
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}
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/* Restore the disable_timing for the SB outputs on the path */
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/*fprintf(fp, "# Restore disable timing for the following Switch Block output:\n");
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