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Fix when explicit verilog is NOT used

This commit is contained in:
Baudouin Chauviere 2019-07-12 10:39:31 -06:00
parent 40d3460bac
commit a0f1f8d163
2 changed files with 10 additions and 11 deletions
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10
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
View File

@ -370,7 +370,7 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp,
port_prefix, pb_type_port->name);
} else {
if (TRUE == dump_explicit_port_map) {
fprintf(fp, ".%s(",
fprintf(fp, ".%s (",
pb_type_port->spice_model_port->lib_name);
}
if (1 < pb_type_port->num_pins) {
@ -445,7 +445,7 @@ void dump_verilog_pb_type_bus_ports(FILE* fp,
}
}
dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "inout",
pb_type_inout_ports[iport], dump_port_type, TRUE);
pb_type_inout_ports[iport], dump_port_type, dump_explicit_port_map);
/* Update the counter */
num_dumped_port++;
@ -464,7 +464,7 @@ void dump_verilog_pb_type_bus_ports(FILE* fp,
}
}
dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "input",
pb_type_input_ports[iport], dump_port_type, TRUE);
pb_type_input_ports[iport], dump_port_type, dump_explicit_port_map);
/* Update the counter */
num_dumped_port++;
}
@ -482,7 +482,7 @@ void dump_verilog_pb_type_bus_ports(FILE* fp,
}
}
dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "output",
pb_type_output_ports[iport], dump_port_type, TRUE);
pb_type_output_ports[iport], dump_port_type, dump_explicit_port_map);
/* Update the counter */
num_dumped_port++;
}
@ -501,7 +501,7 @@ void dump_verilog_pb_type_bus_ports(FILE* fp,
}
}
dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "input",
pb_type_clk_ports[iport], dump_port_type, TRUE);
pb_type_clk_ports[iport], dump_port_type, dump_explicit_port_map);
/* Update the counter */
num_dumped_port++;
}

11
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c
View File

@ -184,7 +184,6 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_sram - 1);
}
if (0 < num_sram_port) {
switch (cur_sram_orgz_info->type) {
case SPICE_SRAM_MEMORY_BANK:
@ -243,7 +242,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
assert(NULL != pad_ports[0]);
/* Add explicit port mapping if required */
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
fprintf(fp, ".%s (",
pad_ports[0]->lib_name);
}
/* Print inout port */
@ -266,7 +265,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
&& (true == is_explicit_mapping)) {
assert( 1 == num_sram_port);
assert( NULL != sram_ports[0]);
fprintf(fp, ".%s(",
fprintf(fp, ".%s (",
sram_ports[0]->lib_name);
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
@ -287,7 +286,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
&& (true == is_explicit_mapping)) {
assert( 1 == num_sram_port);
assert( NULL != sram_ports[0]);
fprintf(fp, ".%s(",
fprintf(fp, ".%s (",
sram_ports[0]->inv_prefix);
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
@ -304,7 +303,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
&& (true == is_explicit_mapping)) {
assert( 1 == num_sram_port);
assert( NULL != sram_ports[0]);
fprintf(fp, ".%s(",
fprintf(fp, ".%s (",
sram_ports[0]->lib_name);
}
dump_verilog_sram_one_outport(fp, cur_sram_orgz_info,
@ -324,7 +323,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
&& (true == is_explicit_mapping)) {
assert( 1 == num_sram_port);
assert( NULL != sram_ports[0]);
fprintf(fp, ".%s(",
fprintf(fp, ".%s (",
sram_ports[0]->inv_prefix);
}
dump_verilog_sram_one_outport(fp, cur_sram_orgz_info,