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Modified code for cleaner delay naming convention

This commit is contained in:
Baudouin Chauviere 2019-05-06 12:52:49 -06:00
parent e7b1d89985
commit a5a1a376ab
4 changed files with 58 additions and 58 deletions
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16
vpr7_x2p/libarchfpga/SRC/include/physical_types.h
View File

@ -319,10 +319,10 @@ struct s_interconnect {
char *output_string;
/* Baudouin Chauviere: SDC generation */
char *loop_breaker_string;
char *loop_breaker_delay_first_segment_min;
char *loop_breaker_delay_first_segment_max;
char *loop_breaker_delay_second_segment_min;
char *loop_breaker_delay_second_segment_max;
char *loop_breaker_delay_before_min;
char *loop_breaker_delay_before_max;
char *loop_breaker_delay_after_min;
char *loop_breaker_delay_after_max;
/* END */
t_pin_to_pin_annotation *annotations; /* [0..num_annotations-1] */
@ -549,10 +549,10 @@ struct s_pb_graph_edge {
boolean is_disabled;
int nb_mux;
int nb_pin;
char* delay_first_segment_max;
char* delay_second_segment_max;
char* delay_first_segment_min;
char* delay_second_segment_min;
char* loop_breaker_delay_before_max;
char* loop_breaker_delay_after_max;
char* loop_breaker_delay_before_min;
char* loop_breaker_delay_after_min;
/* END */
};
typedef struct s_pb_graph_edge t_pb_graph_edge;

12
vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c
View File

@ -1412,30 +1412,30 @@ static void ProcessInterconnect(INOUTP ezxml_t Parent, t_mode * mode) {
}
ezxml_set_attr(Cur, "loop_breaker", NULL);
Cur2 = FindFirstElement(Cur, "delay_first_segment", FALSE);
Cur2 = FindFirstElement(Cur, "loop_breaker_delay_before", FALSE);
if (NULL != Cur2) {
Prop = FindProperty(Cur2, "min", FALSE);
if (NULL != Prop) {
mode->interconnect[i].loop_breaker_delay_first_segment_min = my_strdup(Prop);
mode->interconnect[i].loop_breaker_delay_before_min = my_strdup(Prop);
ezxml_set_attr(Cur2, "min", NULL);
}
Prop = FindProperty(Cur2, "max", FALSE);
if (NULL != Prop) {
mode->interconnect[i].loop_breaker_delay_first_segment_max = my_strdup(Prop);
mode->interconnect[i].loop_breaker_delay_before_max = my_strdup(Prop);
ezxml_set_attr(Cur2, "max", NULL);
}
FreeNode(Cur2);
}
Cur2 = FindFirstElement(Cur, "delay_second_segment", FALSE);
Cur2 = FindFirstElement(Cur, "loop_breaker_delay_after", FALSE);
if (NULL != Cur2) {
Prop = FindProperty(Cur2, "min", FALSE);
if (NULL != Prop) {
mode->interconnect[i].loop_breaker_delay_second_segment_min = my_strdup(Prop);
mode->interconnect[i].loop_breaker_delay_after_min = my_strdup(Prop);
ezxml_set_attr(Cur2, "min", NULL);
}
Prop = FindProperty(Cur2, "max", FALSE);
if (NULL != Prop) {
mode->interconnect[i].loop_breaker_delay_second_segment_max = my_strdup(Prop);
mode->interconnect[i].loop_breaker_delay_after_max = my_strdup(Prop);
ezxml_set_attr(Cur2, "max", NULL);
}
FreeNode(Cur2);

16
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc_pb_types.c
View File

@ -251,22 +251,22 @@ void dump_sdc_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info,
sprintf(set_disable_path, "%s/%s_%d_", input_buffer_path, input_buffer_name,
des_pb_graph_pin->input_edges[iedge]->nb_pin);
if (NULL != des_pb_graph_pin->input_edges[iedge]->delay_first_segment_min) {
if (NULL != des_pb_graph_pin->input_edges[iedge]->loop_breaker_delay_before_min) {
fprintf (fp, "set_min_delay -from %s -to %s/%s %s \n", from_path, set_disable_path, input_buffer_in,
des_pb_graph_pin->input_edges[iedge]->delay_first_segment_min);
des_pb_graph_pin->input_edges[iedge]->loop_breaker_delay_before_min);
}
if (NULL != des_pb_graph_pin->input_edges[iedge]->delay_first_segment_max) {
if (NULL != des_pb_graph_pin->input_edges[iedge]->loop_breaker_delay_before_max) {
fprintf (fp, "set_max_delay -from %s -to %s/%s %s \n", from_path, set_disable_path, input_buffer_in,
des_pb_graph_pin->input_edges[iedge]->delay_first_segment_max);
des_pb_graph_pin->input_edges[iedge]->loop_breaker_delay_before_max);
}
fprintf (fp, "set_disable_timing -from %s -to %s %s \n", input_buffer_in, input_buffer_out, set_disable_path);
if (NULL != des_pb_graph_pin->input_edges[iedge]->delay_second_segment_min) {
if (NULL != des_pb_graph_pin->input_edges[iedge]->loop_breaker_delay_after_min) {
fprintf (fp, "set_min_delay -from %s/%s -to %s %s \n", set_disable_path, input_buffer_out,
to_path, des_pb_graph_pin->input_edges[iedge]->delay_second_segment_min);
to_path, des_pb_graph_pin->input_edges[iedge]->loop_breaker_delay_after_min);
}
if (NULL != des_pb_graph_pin->input_edges[iedge]->delay_second_segment_max) {
if (NULL != des_pb_graph_pin->input_edges[iedge]->loop_breaker_delay_after_max) {
fprintf (fp, "set_max_delay -from %s/%s -to %s %s \n", set_disable_path, input_buffer_out,
to_path, des_pb_graph_pin->input_edges[iedge]->delay_second_segment_max);
to_path, des_pb_graph_pin->input_edges[iedge]->loop_breaker_delay_after_max);
}
my_free(input_buffer_path);
my_free(set_disable_path);

72
vpr7_x2p/vpr/SRC/pack/pb_type_graph.c
View File

@ -2071,21 +2071,21 @@ static void map_loop_breaker_onto_edges(char* loop_breaker_string, int line_num,
if (cur_interc == cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->interconnect) {
cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->is_disabled = TRUE;
if (NULL != cur_interc->loop_breaker_delay_first_segment_min) {
cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_first_segment_min
= cur_interc->loop_breaker_delay_first_segment_min;
if (NULL != cur_interc->loop_breaker_delay_before_min) {
cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_before_min
= cur_interc->loop_breaker_delay_before_min;
}
if (NULL != cur_interc->loop_breaker_delay_first_segment_max) {
cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_first_segment_max
= cur_interc->loop_breaker_delay_first_segment_max;
if (NULL != cur_interc->loop_breaker_delay_before_max) {
cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_before_max
= cur_interc->loop_breaker_delay_before_max;
}
if (NULL != cur_interc->loop_breaker_delay_second_segment_min) {
cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_second_segment_min
= cur_interc->loop_breaker_delay_second_segment_min;
if (NULL != cur_interc->loop_breaker_delay_after_min) {
cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_after_min
= cur_interc->loop_breaker_delay_after_min;
}
if (NULL != cur_interc->loop_breaker_delay_second_segment_max) {
cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_second_segment_max
= cur_interc->loop_breaker_delay_second_segment_max;
if (NULL != cur_interc->loop_breaker_delay_after_max) {
cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_after_max
= cur_interc->loop_breaker_delay_after_max;
}
}
}
@ -2097,21 +2097,21 @@ static void map_loop_breaker_onto_edges(char* loop_breaker_string, int line_num,
if (cur_interc == cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->interconnect) {
cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->is_disabled = TRUE;
if (NULL != cur_interc->loop_breaker_delay_first_segment_min) {
cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_first_segment_min
= cur_interc->loop_breaker_delay_first_segment_min;
if (NULL != cur_interc->loop_breaker_delay_before_min) {
cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_before_min
= cur_interc->loop_breaker_delay_before_min;
}
if (NULL != cur_interc->loop_breaker_delay_first_segment_max) {
cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_first_segment_max
= cur_interc->loop_breaker_delay_first_segment_max;
if (NULL != cur_interc->loop_breaker_delay_before_max) {
cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_before_max
= cur_interc->loop_breaker_delay_before_max;
}
if (NULL != cur_interc->loop_breaker_delay_second_segment_min) {
cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_second_segment_min
= cur_interc->loop_breaker_delay_second_segment_min;
if (NULL != cur_interc->loop_breaker_delay_after_min) {
cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_after_min
= cur_interc->loop_breaker_delay_after_min;
}
if (NULL != cur_interc->loop_breaker_delay_second_segment_max) {
cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_second_segment_max
= cur_interc->loop_breaker_delay_second_segment_max;
if (NULL != cur_interc->loop_breaker_delay_after_max) {
cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_after_max
= cur_interc->loop_breaker_delay_after_max;
}
}
}
@ -2123,21 +2123,21 @@ static void map_loop_breaker_onto_edges(char* loop_breaker_string, int line_num,
if (cur_interc == cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->interconnect) {
cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->is_disabled = TRUE;
if (NULL != cur_interc->loop_breaker_delay_first_segment_min) {
cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_first_segment_min
= cur_interc->loop_breaker_delay_first_segment_min;
if (NULL != cur_interc->loop_breaker_delay_before_min) {
cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_before_min
= cur_interc->loop_breaker_delay_before_min;
}
if (NULL != cur_interc->loop_breaker_delay_first_segment_max) {
cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_first_segment_max
= cur_interc->loop_breaker_delay_first_segment_max;
if (NULL != cur_interc->loop_breaker_delay_before_max) {
cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_before_max
= cur_interc->loop_breaker_delay_before_max;
}
if (NULL != cur_interc->loop_breaker_delay_second_segment_min) {
cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_second_segment_min
= cur_interc->loop_breaker_delay_second_segment_min;
if (NULL != cur_interc->loop_breaker_delay_after_min) {
cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_after_min
= cur_interc->loop_breaker_delay_after_min;
}
if (NULL != cur_interc->loop_breaker_delay_second_segment_max) {
cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_second_segment_max
= cur_interc->loop_breaker_delay_second_segment_max;
if (NULL != cur_interc->loop_breaker_delay_after_max) {
cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_after_max
= cur_interc->loop_breaker_delay_after_max;
}
}
}