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Latest version, not stable yet but close

This commit is contained in:
Baudouin Chauviere 2019-07-09 08:34:01 -06:00
parent df0a3d23a3
commit 25f5bc7792
10 changed files with 1514 additions and 1272 deletions
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2507
vpr7_x2p/libarchfpga/tags
View File

File diff suppressed because it is too large Load Diff

29
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
View File

@ -378,7 +378,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
/* I/O PAD */
dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix,
0, phy_block_type->capacity * phy_block_type->pb_type->physical_mode_num_iopads - 1,
VERILOG_PORT_INOUT, is_explicit_mapping);
VERILOG_PORT_INOUT, false);
/* Print configuration ports */
/* Reserved configuration ports */
@ -622,9 +622,9 @@ void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info,
}
if (IO_TYPE == grid[ix][iy].type) {
dump_verilog_io_grid_pins(fp, ix, iy, TRUE, FALSE, FALSE);
dump_verilog_io_grid_pins(fp, ix, iy, TRUE, border_side, FALSE, FALSE, is_explicit_mapping);
} else {
dump_verilog_grid_pins(fp, ix, iy, TRUE, FALSE, FALSE);
dump_verilog_grid_pins(fp, ix, iy, TRUE, FALSE, FALSE, is_explicit_mapping);
}
/* IO PAD */
@ -792,10 +792,20 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz
fprintf(fp, "//----- %s side channel ports-----\n", side_manager.c_str());
for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) {
fprintf(fp, "%s,\n",
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack),
chan_coordinator.get_x(), chan_coordinator.get_y(), itrack,
rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)));
}
fprintf(fp, "%s",
gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack),
chan_coordinator.get_x(), chan_coordinator.get_y(), itrack,
rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)));
if (true == is_explicit_mapping) {
fprintf(fp, ")",itrack);
}
fprintf(fp, ",\n",itrack);
}
fprintf(fp, "//----- %s side inputs: CLB output pins -----\n", convert_side_index_to_string(side));
/* Dump OPINs of adjacent CLBs */
@ -917,9 +927,16 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_
fprintf(fp, "//----- %s side inputs: channel track middle outputs -----\n",
convert_side_index_to_string(rr_gsb.get_cb_chan_side(cb_type)));
for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) {
fprintf(fp, "%s, ",
if (true == is_explicit_mapping) {
fprintf(fp, ".%s (",
rr_gsb.gen_cb_verilog_routing_track_name(cb_type, itrack));
fprintf(fp, "\n");
}
fprintf(fp, "%s",
rr_gsb.gen_cb_verilog_routing_track_name(cb_type, itrack));
if (true == is_explicit_mapping) {
fprintf(fp, ")",itrack);
}
fprintf(fp, ",\n");
}
std::vector<enum e_side> cb_sides = rr_gsb.get_cb_ipin_sides(cb_type);

116
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
View File

@ -369,8 +369,7 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp,
pb_type_port->num_pins - 1,
port_prefix, pb_type_port->name);
} else {
if ((NULL != cur_pb_type->spice_model)
&& (TRUE == dump_explicit_port_map)) {
if (TRUE == dump_explicit_port_map) {
fprintf(fp, ".%s(",
pb_type_port->spice_model_port->lib_name);
}
@ -383,8 +382,7 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp,
gen_verilog_one_pb_type_pin_name(port_prefix, pb_type_port, ipin));
}
fprintf(fp, "}");
if ((NULL != cur_pb_type->spice_model)
&& (TRUE == dump_explicit_port_map)) {
if (TRUE == dump_explicit_port_map) {
fprintf(fp, ")");
}
}
@ -537,7 +535,8 @@ void dump_verilog_pb_type_ports(FILE* fp,
t_pb_type* cur_pb_type,
boolean dump_port_type,
boolean dump_last_comma,
boolean require_explicit_port_map) {
boolean require_explicit_port_map,
bool is_full_name) {
int iport, ipin;
int num_pb_type_input_port = 0;
t_port** pb_type_input_ports = NULL;
@ -588,18 +587,21 @@ void dump_verilog_pb_type_ports(FILE* fp,
}
if (TRUE == dump_port_type) {
fprintf(fp, "inout wire ");
} else if ((NULL != cur_pb_type->spice_model)
&& (TRUE == require_explicit_port_map)
&& (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) {
} else if (TRUE == require_explicit_port_map) {
if (false == is_full_name && NULL != cur_pb_type->spice_model) {
fprintf(fp, ".%s(",
pb_type_inout_ports[iport]->spice_model_port->lib_name);
} else {
/* fprintf(fp, ".%s(",
gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_inout_ports[iport], ipin)); */
fprintf(fp, ".%s__%s_%d_(",
cur_pb_type->name, pb_type_inout_ports[iport]->name, ipin);
}
}
fprintf(fp, "%s",
fprintf(fp, "%s",
gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_inout_ports[iport], ipin));
if ((FALSE == dump_port_type)
&& (NULL != cur_pb_type->spice_model)
&& (TRUE == require_explicit_port_map)
&& (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) {
if ((FALSE == dump_port_type)
&& TRUE == require_explicit_port_map) {
fprintf(fp, ") ");
}
/* Update the counter */
@ -631,18 +633,21 @@ void dump_verilog_pb_type_ports(FILE* fp,
}
if (TRUE == dump_port_type) {
fprintf(fp, "input wire ");
} else if ((NULL != cur_pb_type->spice_model)
&& (TRUE == require_explicit_port_map)
&& (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) {
} else if (TRUE == require_explicit_port_map) {
if (false == is_full_name && NULL != cur_pb_type->spice_model) {
fprintf(fp, ".%s(",
pb_type_input_ports[iport]->spice_model_port->lib_name);
} else {
/* fprintf(fp, ".%s(",
gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_input_ports[iport], ipin)); */
fprintf(fp, ".%s__%s_%d_(",
cur_pb_type->name, pb_type_input_ports[iport]->name, ipin);
}
}
fprintf(fp, "%s",
gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_input_ports[iport], ipin));
if ((FALSE == dump_port_type)
&& (NULL != cur_pb_type->spice_model)
&& (TRUE == require_explicit_port_map)
&& (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) {
&& TRUE == require_explicit_port_map) {
fprintf(fp, ") ");
}
/* Update the counter */
@ -673,18 +678,21 @@ void dump_verilog_pb_type_ports(FILE* fp,
}
if (TRUE == dump_port_type) {
fprintf(fp, "output wire ");
} else if ((NULL != cur_pb_type->spice_model)
&& (TRUE == require_explicit_port_map)
&& (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) {
} else if (TRUE == require_explicit_port_map) {
if (false == is_full_name && NULL != cur_pb_type->spice_model) {
fprintf(fp, ".%s(",
pb_type_output_ports[iport]->spice_model_port->lib_name);
} else {
/* fprintf(fp, ".%s(",
gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_output_ports[iport], ipin));*/
fprintf(fp, ".%s__%s_%d_(",
cur_pb_type->name, pb_type_output_ports[iport]->name, ipin);
}
}
fprintf(fp, "%s",
gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_output_ports[iport], ipin));
if ((FALSE == dump_port_type)
&& (NULL != cur_pb_type->spice_model)
&& (TRUE == require_explicit_port_map)
&& (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) {
&& TRUE == require_explicit_port_map) {
fprintf(fp, ") ");
}
/* Update the counter */
@ -718,18 +726,19 @@ void dump_verilog_pb_type_ports(FILE* fp,
}
if (TRUE == dump_port_type) {
fprintf(fp, "input wire ");
} else if ((NULL != cur_pb_type->spice_model)
&& (TRUE == require_explicit_port_map)
&& (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) {
} else if (TRUE == require_explicit_port_map) {
if (false == is_full_name && NULL != cur_pb_type->spice_model) {
fprintf(fp, ".%s(",
pb_type_clk_ports[iport]->spice_model_port->lib_name);
} else {
fprintf(fp, ".%s__%s_%d_(",
cur_pb_type->name, pb_type_clk_ports[iport]->name, ipin);
}
}
fprintf(fp, "%s",
gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_clk_ports[iport], ipin));
if ((FALSE == dump_port_type)
&& (NULL != cur_pb_type->spice_model)
&& (TRUE == require_explicit_port_map)
&& (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) {
&& TRUE == require_explicit_port_map) {
fprintf(fp, ") ");
}
/* Update the counter */
@ -1501,7 +1510,7 @@ void dump_verilog_pb_graph_primitive_node(FILE* fp,
fprintf(fp, "module %s (", subckt_name);
/* subckt_port_name = format_verilog_node_prefix(subckt_name); */
/* Inputs, outputs, inouts, clocks */
dump_verilog_pb_type_ports(fp, subckt_name, 0, cur_pb_type, TRUE, FALSE, FALSE);
dump_verilog_pb_type_ports(fp, subckt_name, 0, cur_pb_type, TRUE, FALSE, FALSE, false);
/* SRAM ports */
fprintf(fp, ");\n");
/* Include the spice_model*/
@ -1509,7 +1518,7 @@ void dump_verilog_pb_graph_primitive_node(FILE* fp,
verilog_model->cnt++; /* Stats the number of verilog_model used*/
/* Make input, output, inout, clocks connected*/
/* IMPORTANT: (sequence of these ports should be changed!) */
dump_verilog_pb_type_ports(fp, subckt_name, 0, cur_pb_type, FALSE, FALSE, TRUE);
dump_verilog_pb_type_ports(fp, subckt_name, 0, cur_pb_type, FALSE, FALSE, TRUE, true);
fprintf(fp, ");");
/* Print end of subckt*/
fprintf(fp, "endmodule\n");
@ -1735,12 +1744,12 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, ",\n");
}
/* Simplify the port prefix, make SPICE netlist readable */
dump_verilog_pb_type_ports(fp, subckt_port_prefix, 0, cur_pb_type, TRUE, FALSE, FALSE);
dump_verilog_pb_type_ports(fp, subckt_port_prefix, 0, cur_pb_type, TRUE, FALSE, FALSE, false);
/* Print Input Pad and Output Pad */
dump_verilog_grid_common_port(fp, iopad_verilog_model,
gio_inout_prefix,
stamped_iopad_cnt, iopad_verilog_model->cnt - 1,
VERILOG_PORT_INOUT, is_explicit_mapping);
VERILOG_PORT_INOUT, false);
/* Print Configuration ports */
/* sram_verilog_model->cnt should be updated because all the child pbs have been dumped
* stamped_sram_cnt remains the old sram_verilog_model->cnt before all the child pbs are dumped
@ -1823,7 +1832,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
} else {
if (0 < rec_dump_verilog_spice_model_global_ports(fp,
cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model,
FALSE, TRUE, FALSE)) {
FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
}
@ -1840,7 +1849,13 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
/* Print inputs, outputs, inouts, clocks
* NO SRAMs !!! They have already been fixed in the bottom level
*/
dump_verilog_pb_type_ports(fp, child_pb_type_prefix, 0, &(cur_pb_type->modes[mode_index].pb_type_children[ipb]), FALSE, FALSE, FALSE);
bool is_explicit_full_name = true;
if (NULL != cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model){
if (SPICE_MODEL_HARDLOGIC == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model->type){
is_explicit_full_name = false;
}
}
dump_verilog_pb_type_ports(fp, child_pb_type_prefix, 0, &(cur_pb_type->modes[mode_index].pb_type_children[ipb]), FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), is_explicit_full_name);
/* Print I/O pads */
dump_verilog_grid_common_port(fp, iopad_verilog_model,
gio_inout_prefix,
@ -1871,7 +1886,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
stamped_sram_cnt,
stamped_sram_cnt + child_pb_num_conf_bits - 1,
VERILOG_PORT_CONKT, false);
VERILOG_PORT_CONKT, is_explicit_mapping);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -2008,7 +2023,8 @@ void dump_verilog_grid_pins(FILE* fp,
int y,
boolean top_level,
boolean dump_port_type,
boolean dump_last_comma) {
boolean dump_last_comma,
bool is_explicit_mapping) {
int iheight, side, ipin, class_id;
int side_pin_index;
t_type_ptr type_descriptor = grid[x][y].type;
@ -2063,7 +2079,14 @@ void dump_verilog_grid_pins(FILE* fp,
}
}
/* This pin appear at this side! */
if (true == is_explicit_mapping) {
fprintf(fp, ".%s_height_%d__pin_%d_(",
convert_side_index_to_string(side), iheight, ipin);
}
fprintf(fp, " %s", gen_verilog_grid_one_pin_name(x, y, iheight, side, ipin, top_level));
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
/* Update counter */
num_dumped_port++;
side_pin_index++;
@ -2093,8 +2116,10 @@ void dump_verilog_grid_pins(FILE* fp,
void dump_verilog_io_grid_pins(FILE* fp,
int x, int y,
boolean top_level,
int border_side,
boolean dump_port_type,
boolean dump_last_comma) {
boolean dump_last_comma,
bool is_explicit_mapping) {
int iheight, side, ipin;
int side_pin_index;
t_type_ptr type_descriptor = grid[x][y].type;
@ -2156,7 +2181,14 @@ void dump_verilog_io_grid_pins(FILE* fp,
}
}
/* This pin appear at this side! */
if (true == is_explicit_mapping) {
fprintf(fp, ".%s_height_%d__pin_%d_(",
convert_side_index_to_string(border_side), iheight, ipin);
}
fprintf(fp, " %s", gen_verilog_grid_one_pin_name(x, y, iheight, side, ipin, top_level));
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
/* Update counter */
num_dumped_port++;
side_pin_index++;
@ -2581,9 +2613,9 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info,
/* Pins */
/* Special Care for I/O grid */
if (IO_TYPE == grid[ix][iy].type) {
dump_verilog_io_grid_pins(fp, ix, iy, FALSE, TRUE, FALSE);
dump_verilog_io_grid_pins(fp, ix, iy, FALSE, 0, TRUE, FALSE,is_explicit_mapping);
} else {
dump_verilog_grid_pins(fp, ix, iy, FALSE, TRUE, FALSE);
dump_verilog_grid_pins(fp, ix, iy, FALSE, TRUE, FALSE, is_explicit_mapping);
}
/* IO PAD */

10
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h
View File

@ -32,7 +32,8 @@ void dump_verilog_pb_type_ports(FILE* fp,
t_pb_type* cur_pb_type,
boolean dump_port_type,
boolean dump_last_comma,
boolean require_explicit_port_map);
boolean require_explicit_port_map,
bool is_full_name);
void dump_verilog_dangling_des_pb_graph_pin_interc(FILE* fp,
t_pb_graph_pin* des_pb_graph_pin,
@ -111,13 +112,16 @@ void dump_verilog_grid_pins(FILE* fp,
int x, int y,
boolean top_level,
boolean dump_port_type,
boolean dump_last_comma);
boolean dump_last_comma,
bool is_explicit_mapping);
void dump_verilog_io_grid_pins(FILE* fp,
int x, int y,
boolean top_level,
int border_side,
boolean dump_port_type,
boolean dump_last_comma);
boolean dump_last_comma,
bool is_explicit_mapping);
char* get_grid_block_subckt_name(int x,
int y,

28
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c
View File

@ -134,8 +134,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_bl, &cur_wl);
/* print ports --> input ports */
dump_verilog_pb_type_ports(fp, port_prefix, 0, prim_pb_type, TRUE, FALSE, FALSE);
dump_verilog_pb_type_ports(fp, port_prefix, 0, prim_pb_type, TRUE, FALSE, FALSE, false);
/* IOPADs requires a specical port to output */
if (SPICE_MODEL_IOPAD == verilog_model->type) {
fprintf(fp, ",\n");
@ -236,22 +235,21 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
/* assert */
num_sram = count_num_sram_bits_one_spice_model(verilog_model, -1);
/* print ports --> input ports */
dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, prim_pb_type, FALSE, FALSE, verilog_model->dump_explicit_port_map);
dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, prim_pb_type, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping));
/* IOPADs requires a specical port to output */
if (SPICE_MODEL_IOPAD == verilog_model->type) {
fprintf(fp, ",\n");
assert(1 == num_pad_port);
assert(NULL != pad_ports[0]);
/* Add explicit port mapping if required */
if (TRUE == verilog_model->dump_explicit_port_map) {
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
pad_ports[0]->lib_name);
}
/* Print inout port */
fprintf(fp, "%s%s[%d]", gio_inout_prefix,
verilog_model->prefix, verilog_model->cnt);
if (TRUE == verilog_model->dump_explicit_port_map) {
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
@ -265,7 +263,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
case SPICE_SRAM_SCAN_CHAIN:
/* Add explicit port mapping if required */
if ( (0 < num_sram)
&& (TRUE == verilog_model->dump_explicit_port_map)) {
&& (true == is_explicit_mapping)) {
assert( 1 == num_sram_port);
assert( NULL != sram_ports[0]);
fprintf(fp, ".%s(",
@ -275,7 +273,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_sram - 1,
0, VERILOG_PORT_CONKT);
if ( (0 < num_sram)
&& (TRUE == verilog_model->dump_explicit_port_map)) {
&& (true == is_explicit_mapping)) {
fprintf(fp, ")");
}
@ -286,7 +284,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, ", ");
/* Add explicit port mapping if required */
if ( (0 < num_sram)
&& (TRUE == verilog_model->dump_explicit_port_map)) {
&& (true == is_explicit_mapping)) {
assert( 1 == num_sram_port);
assert( NULL != sram_ports[0]);
fprintf(fp, ".%s(",
@ -296,14 +294,14 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_sram - 1,
1, VERILOG_PORT_CONKT);
if ( (0 < num_sram)
&& (TRUE == verilog_model->dump_explicit_port_map)) {
&& (true == is_explicit_mapping)) {
fprintf(fp, ")");
}
break;
case SPICE_SRAM_MEMORY_BANK:
/* Add explicit port mapping if required */
if ( (0 < num_sram)
&& (TRUE == verilog_model->dump_explicit_port_map)) {
&& (true == is_explicit_mapping)) {
assert( 1 == num_sram_port);
assert( NULL != sram_ports[0]);
fprintf(fp, ".%s(",
@ -313,7 +311,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_sram - 1,
0, VERILOG_PORT_CONKT);
if ( (0 < num_sram)
&& (TRUE == verilog_model->dump_explicit_port_map)) {
&& (true == is_explicit_mapping)) {
fprintf(fp, ")");
}
/* Check if we have an inverterd prefix */
@ -323,7 +321,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, ", ");
/* Add explicit port mapping if required */
if ( (0 < num_sram)
&& (TRUE == verilog_model->dump_explicit_port_map)) {
&& (true == is_explicit_mapping)) {
assert( 1 == num_sram_port);
assert( NULL != sram_ports[0]);
fprintf(fp, ".%s(",
@ -333,7 +331,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_sram - 1,
1, VERILOG_PORT_CONKT);
if ( (0 < num_sram)
&& (TRUE == verilog_model->dump_explicit_port_map)) {
&& (true == is_explicit_mapping)) {
fprintf(fp, ")");
}
break;
@ -531,7 +529,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, ",\n");
}
/* Print inputs, outputs, inouts, clocks, NO SRAMs*/
dump_verilog_pb_type_ports(fp, port_prefix, 0, cur_pb_type, TRUE, TRUE, FALSE);
dump_verilog_pb_type_ports(fp, port_prefix, 0, cur_pb_type, TRUE, TRUE, FALSE, false);
/* Print SRAM ports */
cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info);
get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_bl, &cur_wl);

2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
View File

@ -2101,7 +2101,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
rr_gsb.get_sb_conf_bits_lsb(),
rr_gsb.get_sb_conf_bits_msb(),
VERILOG_PORT_INPUT,
is_explicit_mapping);
false);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}

2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c
View File

@ -3088,7 +3088,7 @@ void dump_verilog_submodule_one_lut(FILE* fp,
input_port[0]->prefix);
/* Connect MUX inverted configuration port to inverted LUT inputs */
if (true == is_explicit_mapping) {
fprintf(fp, "), sram_inv(");
fprintf(fp, "), .sram_inv(");
} else {
fprintf(fp, ", ");
}

25
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c
View File

@ -396,9 +396,9 @@ void dump_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info,
}
if (IO_TYPE == grid[ix][iy].type) {
dump_verilog_io_grid_pins(fp, ix, iy, TRUE, FALSE, FALSE);
dump_verilog_io_grid_pins(fp, ix, iy, TRUE, 0, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping));
} else {
dump_verilog_grid_pins(fp, ix, iy, TRUE, FALSE, FALSE);
dump_verilog_grid_pins(fp, ix, iy, TRUE, FALSE, FALSE, is_explicit_mapping);
}
/* IO PAD */
@ -1474,8 +1474,15 @@ void dump_compact_verilog_io_grid_block_subckt_pins(FILE* fp,
if (0 < dump_pin_cnt) {
fprintf(fp, ",\n");
}
if (true == is_explicit_mapping) {
fprintf(fp, ".%s (",
gen_verilog_one_pb_type_pin_name(chomp_verilog_prefix(top_pb_graph_node->pb_type->name), top_pb_graph_node->input_pins[iport]->port, ipin));
}
fprintf(fp, "%s_height_%d__pin_%d_",
convert_side_index_to_string(border_side), pin_height, grid_pin_index);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
side_pin_index++;
dump_pin_cnt++;
}
@ -1497,8 +1504,15 @@ void dump_compact_verilog_io_grid_block_subckt_pins(FILE* fp,
if (0 < dump_pin_cnt) {
fprintf(fp, ",\n");
}
if (true == is_explicit_mapping) {
fprintf(fp, ".%s (",
gen_verilog_one_pb_type_pin_name(chomp_verilog_prefix(top_pb_graph_node->pb_type->name), top_pb_graph_node->output_pins[iport]->port, ipin));
}
fprintf(fp, "%s_height_%d__pin_%d_",
convert_side_index_to_string(border_side), pin_height, grid_pin_index);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
side_pin_index++;
dump_pin_cnt++;
}
@ -1520,8 +1534,15 @@ void dump_compact_verilog_io_grid_block_subckt_pins(FILE* fp,
if (0 < dump_pin_cnt) {
fprintf(fp, ",\n");
}
if (true == is_explicit_mapping) {
fprintf(fp, ".%s (",
gen_verilog_one_pb_type_pin_name(chomp_verilog_prefix(top_pb_graph_node->pb_type->name), top_pb_graph_node->clock_pins[iport]->port, ipin));
}
fprintf(fp, "%s_height_%d__pin_%d_",
convert_side_index_to_string(border_side), pin_height, grid_pin_index);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
side_pin_index++;
dump_pin_cnt++;
}

65
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c
View File

@ -806,16 +806,14 @@ int rec_dump_verilog_spice_model_lib_global_ports(FILE* fp,
cur_spice_model_port->lib_name);
} else {
/* Add explicit port mapping if required */
if ((TRUE == require_explicit_port_map)
&& (TRUE == cur_spice_model->dump_explicit_port_map)) {
if (TRUE == require_explicit_port_map) {
fprintf(fp, ".%s(",
cur_spice_model_port->lib_name);
}
fprintf(fp, "%s[0:%d]",
cur_spice_model_port->lib_name,
cur_spice_model_port->size - 1);
if ((TRUE == require_explicit_port_map)
&& (TRUE == cur_spice_model->dump_explicit_port_map)) {
if (TRUE == require_explicit_port_map) {
fprintf(fp, ")");
}
}
@ -902,8 +900,7 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp,
cur_spice_model_port->prefix);
} else {
/* Add explicit port mapping if required */
if ((TRUE == require_explicit_port_map)
&& (TRUE == cur_spice_model->dump_explicit_port_map)) {
if (TRUE == require_explicit_port_map ) {
fprintf(fp, ".%s(",
/* cur_spice_model_port->lib_name); /* Old version*/
cur_spice_model_port->prefix);
@ -911,8 +908,7 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp,
fprintf(fp, "%s[0:%d]",
cur_spice_model_port->prefix,
cur_spice_model_port->size - 1);
if ((TRUE == require_explicit_port_map)
&& (TRUE == cur_spice_model->dump_explicit_port_map)) {
if (TRUE == require_explicit_port_map) {
fprintf(fp, ")");
}
}
@ -2736,9 +2732,15 @@ void dump_verilog_grid_common_port(FILE* fp, t_spice_model* cur_verilog_model,
/*Malloc and generate the full name of port */
port_full_name = (char*)my_malloc(sizeof(char)*(strlen(general_port_prefix) + strlen(cur_verilog_model->prefix) + 1));
sprintf(port_full_name, "%s%s", general_port_prefix, cur_verilog_model->prefix);
fprintf(fp, ",\n");
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
port_full_name);
}
dump_verilog_generic_port(fp, dump_port_type, port_full_name, msb, lsb);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
/* Free */
/* Local variables such as port1_name and port2 name are automatically freed */
@ -3099,6 +3101,7 @@ void dump_verilog_mem_sram_submodule(FILE* fp,
int num_bl_per_sram = 0;
int num_wl_per_sram = 0;
int iport = 0;
/* Check the file handler*/
if (NULL == fp) {
@ -3201,75 +3204,99 @@ void dump_verilog_mem_sram_submodule(FILE* fp,
if (SPICE_MODEL_MUX == cur_verilog_model->type) {
/* Input of Scan-chain DFF, should be connected to the output of its precedent */
if (true == is_explicit_mapping) {
while(TRUE == cur_sram_verilog_model->ports[iport].is_global) {
iport++;
}
fprintf(fp, ".%s(",
cur_sram_verilog_model->ports[0].prefix);
cur_sram_verilog_model->ports[iport].prefix);
}
dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info,
cur_verilog_model, mux_size,
lsb, msb,
-1, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
iport++;
fprintf(fp, ")");
}
fprintf(fp, ", \n"); //
fprintf(fp, ", \n");
/* Output of Scan-chain DFF, should be connected to the output of its successor */
while(TRUE == cur_sram_verilog_model->ports[iport].is_global) {
iport++;
}
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
cur_sram_verilog_model->ports[1].prefix);
cur_sram_verilog_model->ports[iport].prefix);
}
dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info,
cur_verilog_model, mux_size,
lsb, msb,
0, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
iport++;
fprintf(fp, ")");
}
fprintf(fp, ", \n"); //
fprintf(fp, ", \n");
while(TRUE == cur_sram_verilog_model->ports[iport].is_global) {
iport++;
}
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
cur_sram_verilog_model->ports[2].prefix);
cur_sram_verilog_model->ports[iport].prefix);
}
dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info,
cur_verilog_model, mux_size,
lsb, msb,
1, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
iport++;
fprintf(fp, ")");
}
break;
}
/* Input of Scan-chain DFF, should be connected to the output of its precedent */
if (true == is_explicit_mapping) {
while(TRUE == cur_sram_verilog_model->ports[iport].is_global) {
iport++;
}
fprintf(fp, ".%s(",
cur_sram_verilog_model->ports[0].prefix);
cur_sram_verilog_model->ports[iport].prefix);
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
lsb, msb,
-1, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
iport++;
fprintf(fp, ")");
}
fprintf(fp, ", \n"); //
fprintf(fp, ", \n");
/* Output of Scan-chain DFF, should be connected to the output of its successor */
if (true == is_explicit_mapping) {
while(TRUE == cur_sram_verilog_model->ports[iport].is_global) {
iport++;
}
fprintf(fp, ".%s(",
cur_sram_verilog_model->ports[1].prefix);
cur_sram_verilog_model->ports[iport].prefix);
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
lsb, msb,
0, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
iport++;
fprintf(fp, ")");
}
fprintf(fp, ", \n"); //
fprintf(fp, ", \n");
if (true == is_explicit_mapping) {
while(TRUE == cur_sram_verilog_model->ports[iport].is_global) {
iport++;
}
fprintf(fp, ".%s(",
cur_sram_verilog_model->ports[2].prefix);
cur_sram_verilog_model->ports[iport].prefix);
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
lsb, msb,
1, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
iport++;
fprintf(fp, ")");
}
break;

2
vpr7_x2p/vpr/regression_verilog.sh Normal file → Executable file
View File

@ -35,6 +35,8 @@ cd -
# Run VPR
./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy --fpga_verilog_explicit_mapping
#/research/ece/lnis/USERS/chauviere/wk_Baudouin/OpenFPGA/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml /research/ece/lnis/USERS/chauviere/wk_Baudouin/OpenFPGA/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.blif --full_stats --nodisp --activity_file /research/ece/lnis/USERS/chauviere/wk_Baudouin/OpenFPGA/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.act --fpga_verilog --fpga_verilog_dir /research/ece/lnis/USERS/chauviere/wk_Baudouin/OpenFPGA/vpr7_x2p/vpr/test_modes_Verilog --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench /research/ece/lnis/USERS/chauviere/wk_Baudouin/OpenFPGA/fpga_flow/benchmarks/Verilog/Test_Modes/test_modes.v --fpga_verilog_print_user_defined_template --route_chan_width 200 --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties /research/ece/lnis/USERS/chauviere/wk_Baudouin/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.xml --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy --fpga_verilog_explicit_mapping
cd $fpga_flow_scripts
perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path
cd -