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fixed critical bugs in pass_tracks identification and update regression test for tileable arch

This commit is contained in:
tangxifan 2019-06-25 21:59:38 -06:00
parent 4d3b5f12b4
commit 3c0ef2067d
8 changed files with 30 additions and 16 deletions
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8
vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.cpp
View File

@ -376,16 +376,16 @@ DeviceCoordinator get_track_rr_node_end_coordinator(const t_rr_node* track_rr_no
/* Make sure we have CHANX or CHANY */
assert ( (CHANX == track_rr_node->type) ||(CHANY == track_rr_node->type) );
DeviceCoordinator start_coordinator;
DeviceCoordinator end_coordinator;
if (INC_DIRECTION == track_rr_node->direction) {
start_coordinator.set(track_rr_node->xhigh, track_rr_node->yhigh);
end_coordinator.set(track_rr_node->xhigh, track_rr_node->yhigh);
} else {
assert (DEC_DIRECTION == track_rr_node->direction);
start_coordinator.set(track_rr_node->xlow, track_rr_node->ylow);
end_coordinator.set(track_rr_node->xlow, track_rr_node->ylow);
}
return start_coordinator;
return end_coordinator;
}
/************************************************************************

4
vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp
View File

@ -434,7 +434,7 @@ void load_one_chan_rr_nodes_basic_info(const DeviceCoordinator& chan_coordinator
/* fill fast look-up table */
/* Get node_id */
int track_node_id = chan_details->get_track_node_id(itrack);
/* CHANX requires a reverted (x,y) in the fast look-up table */
/* CHANY requires a reverted (x,y) in the fast look-up table */
if (CHANX == chan_type) {
load_one_node_to_rr_graph_fast_lookup(rr_graph, track_node_id,
chan_type,
@ -442,7 +442,7 @@ void load_one_chan_rr_nodes_basic_info(const DeviceCoordinator& chan_coordinator
chan_coordinator.get_x(),
itrack);
}
/* CHANY follows a regular (x,y) in the fast look-up table */
/* CHANX follows a regular (x,y) in the fast look-up table */
if (CHANY == chan_type) {
load_one_node_to_rr_graph_fast_lookup(rr_graph, track_node_id,
chan_type,

22
vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp
View File

@ -373,7 +373,7 @@ void build_gsb_one_group_track_to_track_map(const t_rr_graph* rr_graph,
/* 2. next side */
/* Next side definition: TOP => RIGHT; RIGHT=>BOTTOM; BOTTOM=>LEFT; LEFT=>TOP */
to_track_sides.push_back(side_manager.get_rotate_clockwise());
for (size_t inode = 0; inode < from_tracks[side].size(); ++inode) {
for (size_t to_side_id = 0; to_side_id < to_track_sides.size(); ++to_side_id) {
enum e_side to_side = to_track_sides[to_side_id];
@ -387,6 +387,7 @@ void build_gsb_one_group_track_to_track_map(const t_rr_graph* rr_graph,
if (from_side == to_side) {
continue;
}
/* Get other track_ids depending on the switch block pattern */
/* Find the track ids that will start at the other sides */
std::vector<size_t> to_track_ids = get_switch_block_to_track_id(sb_type, Fs, from_side, inode,
@ -404,6 +405,11 @@ void build_gsb_one_group_track_to_track_map(const t_rr_graph* rr_graph,
// to_track_index, to_tracks[to_side_index].size());
t_rr_node* to_track_node = rr_gsb.get_chan_node(to_side, to_track_index);
/* from_track should be IN_PORT */
assert( IN_PORT == rr_gsb.get_chan_node_direction(from_side, from_track_index) );
/* to_track should be OUT_PORT */
assert( OUT_PORT == rr_gsb.get_chan_node_direction(to_side, to_track_index) );
/* Check if the to_track_node is already in the list ! */
std::vector<int>::iterator it = std::find((*track2track_map)[from_side_index][from_track_index].begin(),
(*track2track_map)[from_side_index][from_track_index].end(),
@ -491,6 +497,12 @@ t_track2track_map build_gsb_track_to_track_map(const t_rr_graph* rr_graph,
enum e_side gsb_side = side_manager.get_side();
/* Build a list of tracks that will start from this side */
for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) {
/* We need to check Switch block population of this track
* The track node will not be considered if there supposed to be no SB at this position
*/
if (false == is_gsb_in_track_sb_population(rr_gsb, gsb_side, inode, segment_inf)) {
continue; /* skip this node and go to the next */
}
/* check if this track will start from here */
enum e_track_status track_status = determine_track_status_of_gsb(rr_gsb, gsb_side, inode);
switch (track_status) {
@ -503,11 +515,9 @@ t_track2track_map build_gsb_track_to_track_map(const t_rr_graph* rr_graph,
end_tracks[side].push_back(inode);
break;
case TRACK_PASS:
/* We need to check Switch block population of this track
* The track node will not be considered if there supposed to be no SB at this position
*/
if (true == is_gsb_in_track_sb_population(rr_gsb, gsb_side, inode, segment_inf)) {
/* Update passing track list */
/* Update passing track list */
/* Note that the pass_track should be IN_PORT only !!! */
if (IN_PORT == rr_gsb.get_chan_node_direction(gsb_side, inode)) {
pass_tracks[side].push_back(inode);
}
break;

1
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c
View File

@ -1831,6 +1831,7 @@ t_rr_node** get_chan_rr_nodes(int* num_chan_rr_nodes,
chan_rr_nodes = (t_rr_node**)my_malloc((*num_chan_rr_nodes)*sizeof(t_rr_node*));
/* Fill the array */
for (itrack = 0; itrack < (*num_chan_rr_nodes); itrack++) {
/* CHANX follows a weird way in searching rr_nodes */
inode = get_rr_node_index(x, y, CHANX, itrack, LL_rr_node_indices);
chan_rr_nodes[itrack] = &(LL_rr_node[inode]);
}

1
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c
View File

@ -1347,6 +1347,7 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir,
if (TRUE == output_sb_xml) {
create_dir_path(sb_xml_dir);
write_device_rr_gsb_to_xml(sb_xml_dir, LL_device_rr_gsb);
/* Skip rotating mirror searching */

5
vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp
View File

@ -1013,8 +1013,9 @@ bool RRGSB::is_sb_node_imply_short_connection(t_rr_node* src_node) const {
int index;
get_node_side_and_index(src_node->drive_rr_nodes[inode], IN_PORT, &side, &index);
/* We need to be sure that drive_rr_node is part of the SB */
if (((-1 == index) || (NUM_SIDES == side))
&& ((CHANX == src_node->drive_rr_nodes[inode]->type) || (CHANY == src_node->drive_rr_nodes[inode]->type))) {
if ( ((-1 == index) || (NUM_SIDES == side))
&& ( (CHANX == src_node->drive_rr_nodes[inode]->type)
|| (CHANY == src_node->drive_rr_nodes[inode]->type) ) ) {
return true;
}
}

3
vpr7_x2p/vpr/SRC/fpga_x2p/base/write_rr_blocks.cpp
View File

@ -117,6 +117,7 @@ void write_rr_switch_block_to_xml(std::string fname_prefix, RRGSB& rr_gsb) {
enum e_side drive_node_side = NUM_SIDES;
int drive_node_index = -1;
rr_gsb.get_node_side_and_index(drive_rr_nodes[jnode], IN_PORT, &drive_node_side, &drive_node_index);
if (-1 == drive_node_index)
assert(-1 != drive_node_index);
Side drive_side(drive_node_side);
@ -156,7 +157,7 @@ void write_rr_switch_block_to_xml(std::string fname_prefix, RRGSB& rr_gsb) {
/* Output each rr_switch_block to a XML file */
void write_device_rr_gsb_to_xml(char* sb_xml_dir,
DeviceRRGSB& LL_device_rr_gsb) {
DeviceRRGSB& LL_device_rr_gsb) {
std::string fname_prefix(sb_xml_dir);
/* Add slash if needed */
if ('/' != fname_prefix.back()) {

2
vpr7_x2p/vpr/regression_verilog.sh
View File

@ -33,7 +33,7 @@ perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path
cd -
# Run VPR
./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy
./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy --fpga_verilog_print_report_timing_tcl
cd $fpga_flow_scripts
perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path