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Change simulator script generation (waves)

This commit is contained in:
AurelienUoU 2018-12-14 14:40:04 -07:00
parent ee6b1d6cd6
commit 21dc8a006f
3 changed files with 38 additions and 16 deletions
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21
vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_autocheck_tb.c
View File

@ -537,13 +537,18 @@ void dump_verilog_top_auto_testbench_ports(FILE* fp,
assert((VPACK_INPAD == logical_block[iblock].type)||(VPACK_OUTPAD == logical_block[iblock].type));
fprintf(fp, "//----- Blif Benchmark inout %s is mapped to FPGA IOPAD %s[%d] -----\n",
logical_block[iblock].name, gio_inout_prefix, iopad_idx);
fprintf(fp, "wire %s_%s_%d_;\n",
logical_block[iblock].name, gio_inout_prefix, iopad_idx);
fprintf(fp, "assign %s_%s_%d_ = %s%s[%d];\n",
logical_block[iblock].name, gio_inout_prefix, iopad_idx,
gio_inout_prefix, iopad_verilog_model->prefix, iopad_idx);
// AA: Generate wire and reg to autocheck with benchmark
if(VPACK_OUTPAD == logical_block[iblock].type) {
if(VPACK_INPAD == logical_block[iblock].type){
fprintf(fp, "wire in_%s_%s_%d_;\n",
logical_block[iblock].name, gio_inout_prefix, iopad_idx);
fprintf(fp, "assign in_%s_%s_%d_ = %s%s[%d];\n",
logical_block[iblock].name, gio_inout_prefix, iopad_idx,
gio_inout_prefix, iopad_verilog_model->prefix, iopad_idx);
} else{
fprintf(fp, "wire %s_%s_%d_;\n",
logical_block[iblock].name, gio_inout_prefix, iopad_idx);
fprintf(fp, "assign %s_%s_%d_ = %s%s[%d];\n",
logical_block[iblock].name, gio_inout_prefix, iopad_idx,
gio_inout_prefix, iopad_verilog_model->prefix, iopad_idx);
fprintf(fp, "wire %s_benchmark;\n", logical_block[iblock].name);
fprintf(fp, "reg %s_verification;\n", logical_block[iblock].name);
}
@ -571,7 +576,7 @@ void dump_verilog_top_auto_testbench_call_benchmark(FILE* fp, char* blif_circuit
if(TRUE == logical_block[iblock].is_clock){
fprintf(fp, " %s", top_tb_op_clock_port_name);
} else if(VPACK_INPAD == logical_block[iblock].type){
fprintf(fp, " %s_%s_%d_", logical_block[iblock].name, gio_inout_prefix, iopad_idx);
fprintf(fp, " in_%s_%s_%d_", logical_block[iblock].name, gio_inout_prefix, iopad_idx);
} else if(VPACK_OUTPAD == logical_block[iblock].type){
fprintf(fp, " %s_benchmark", logical_block[iblock].name);
}

29
vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_modelsim_autodeck.c
View File

@ -154,7 +154,13 @@ void dump_verilog_modelsim_proc_script(char* modelsim_proc_filename,
fprintf(fp, " \n");
fprintf(fp, "proc add_waves {} {\n");
fprintf(fp, " add wave -position insertpoint sim:/%s/*\n", circuit_top_tb_name);
fprintf(fp, " add wave -position insertpoint sim:/%s/prog_clock \\\n\
sim:/%s/op_clock \\\n\
sim:/%s/in_* \\\n\
sim:/%s/out_*\n", circuit_top_tb_name,
circuit_top_tb_name,
circuit_top_tb_name,
circuit_top_tb_name);
fprintf(fp, "}\n");
@ -286,7 +292,13 @@ void dump_verilog_modelsim_proc_auto_script(char* modelsim_proc_filename,
fprintf(fp, " \n");
fprintf(fp, "proc add_waves {} {\n");
fprintf(fp, " add wave -position insertpoint sim:/%s/*\n", circuit_top_tb_name);
fprintf(fp, " add wave -position insertpoint sim:/%s/prog_clock \\\n\
sim:/%s/op_clock \\\n\
sim:/%s/in_* \\\n\
sim:/%s/out_* \n", circuit_top_tb_name,
circuit_top_tb_name,
circuit_top_tb_name,
circuit_top_tb_name);
fprintf(fp, "}\n");
@ -418,7 +430,13 @@ void dump_verilog_modelsim_proc_auto_preconf_script(char* modelsim_proc_filename
fprintf(fp, " \n");
fprintf(fp, "proc add_waves {} {\n");
fprintf(fp, " add wave -position insertpoint sim:/%s/*\n", circuit_top_tb_name);
fprintf(fp, " add wave -position insertpoint sim:/%s/prog_clock \\\n\
sim:/%s/op_clock \\\n\
sim:/%s/in_* \\\n\
sim:/%s/out_*\n", circuit_top_tb_name,
circuit_top_tb_name,
circuit_top_tb_name,
circuit_top_tb_name);
fprintf(fp, "}\n");
@ -656,9 +674,8 @@ void dump_verilog_modelsim_top_auto_preconf_script(char* modelsim_top_auto_scrip
fprintf(fp, "\n");
fprintf(fp, "#in ms\n");
fprintf(fp, "set simtime %.4g\n", sim_time);
fprintf(fp, "set unit %s\n",
sim_time_unit);
fprintf(fp, "set simtime 150\n");
fprintf(fp, "set unit us\n");
fprintf(fp, "\n");
fprintf(fp, "#Path were both tcl script are located\n");

4
vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_top_netlist.c
View File

@ -1640,9 +1640,9 @@ void dump_verilog_top_testbench_ports(FILE* fp,
assert((VPACK_INPAD == logical_block[iblock].type)||(VPACK_OUTPAD == logical_block[iblock].type));
fprintf(fp, "//----- Blif Benchmark inout %s is mapped to FPGA IOPAD %s[%d] -----\n",
logical_block[iblock].name, gio_inout_prefix, iopad_idx);
fprintf(fp, "wire %s_%s_%d_;\n",
fprintf(fp, "wire in_%s_%s_%d_;\n",
logical_block[iblock].name, gio_inout_prefix, iopad_idx);
fprintf(fp, "assign %s_%s_%d_ = %s%s[%d];\n",
fprintf(fp, "assign in_%s_%s_%d_ = %s%s[%d];\n",
logical_block[iblock].name, gio_inout_prefix, iopad_idx,
gio_inout_prefix, iopad_verilog_model->prefix, iopad_idx);
}