From 21dc8a006f5da44ec76e62fb0ae61275bc23d1ec Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Fri, 14 Dec 2018 14:40:04 -0700 Subject: [PATCH] Change simulator script generation (waves) --- .../fpga_spice/verilog/verilog_autocheck_tb.c | 21 +++++++++----- .../verilog/verilog_modelsim_autodeck.c | 29 +++++++++++++++---- .../fpga_spice/verilog/verilog_top_netlist.c | 4 +-- 3 files changed, 38 insertions(+), 16 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_autocheck_tb.c b/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_autocheck_tb.c index 6d7505882..0cc0f1c83 100644 --- a/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_autocheck_tb.c +++ b/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_autocheck_tb.c @@ -537,13 +537,18 @@ void dump_verilog_top_auto_testbench_ports(FILE* fp, assert((VPACK_INPAD == logical_block[iblock].type)||(VPACK_OUTPAD == logical_block[iblock].type)); fprintf(fp, "//----- Blif Benchmark inout %s is mapped to FPGA IOPAD %s[%d] -----\n", logical_block[iblock].name, gio_inout_prefix, iopad_idx); - fprintf(fp, "wire %s_%s_%d_;\n", - logical_block[iblock].name, gio_inout_prefix, iopad_idx); - fprintf(fp, "assign %s_%s_%d_ = %s%s[%d];\n", - logical_block[iblock].name, gio_inout_prefix, iopad_idx, - gio_inout_prefix, iopad_verilog_model->prefix, iopad_idx); - // AA: Generate wire and reg to autocheck with benchmark - if(VPACK_OUTPAD == logical_block[iblock].type) { + if(VPACK_INPAD == logical_block[iblock].type){ + fprintf(fp, "wire in_%s_%s_%d_;\n", + logical_block[iblock].name, gio_inout_prefix, iopad_idx); + fprintf(fp, "assign in_%s_%s_%d_ = %s%s[%d];\n", + logical_block[iblock].name, gio_inout_prefix, iopad_idx, + gio_inout_prefix, iopad_verilog_model->prefix, iopad_idx); + } else{ + fprintf(fp, "wire %s_%s_%d_;\n", + logical_block[iblock].name, gio_inout_prefix, iopad_idx); + fprintf(fp, "assign %s_%s_%d_ = %s%s[%d];\n", + logical_block[iblock].name, gio_inout_prefix, iopad_idx, + gio_inout_prefix, iopad_verilog_model->prefix, iopad_idx); fprintf(fp, "wire %s_benchmark;\n", logical_block[iblock].name); fprintf(fp, "reg %s_verification;\n", logical_block[iblock].name); } @@ -571,7 +576,7 @@ void dump_verilog_top_auto_testbench_call_benchmark(FILE* fp, char* blif_circuit if(TRUE == logical_block[iblock].is_clock){ fprintf(fp, " %s", top_tb_op_clock_port_name); } else if(VPACK_INPAD == logical_block[iblock].type){ - fprintf(fp, " %s_%s_%d_", logical_block[iblock].name, gio_inout_prefix, iopad_idx); + fprintf(fp, " in_%s_%s_%d_", logical_block[iblock].name, gio_inout_prefix, iopad_idx); } else if(VPACK_OUTPAD == logical_block[iblock].type){ fprintf(fp, " %s_benchmark", logical_block[iblock].name); } diff --git a/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_modelsim_autodeck.c b/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_modelsim_autodeck.c index e0fa4c457..a4872194c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_modelsim_autodeck.c +++ b/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_modelsim_autodeck.c @@ -154,7 +154,13 @@ void dump_verilog_modelsim_proc_script(char* modelsim_proc_filename, fprintf(fp, " \n"); fprintf(fp, "proc add_waves {} {\n"); - fprintf(fp, " add wave -position insertpoint sim:/%s/*\n", circuit_top_tb_name); + fprintf(fp, " add wave -position insertpoint sim:/%s/prog_clock \\\n\ + sim:/%s/op_clock \\\n\ + sim:/%s/in_* \\\n\ + sim:/%s/out_*\n", circuit_top_tb_name, + circuit_top_tb_name, + circuit_top_tb_name, + circuit_top_tb_name); fprintf(fp, "}\n"); @@ -286,7 +292,13 @@ void dump_verilog_modelsim_proc_auto_script(char* modelsim_proc_filename, fprintf(fp, " \n"); fprintf(fp, "proc add_waves {} {\n"); - fprintf(fp, " add wave -position insertpoint sim:/%s/*\n", circuit_top_tb_name); + fprintf(fp, " add wave -position insertpoint sim:/%s/prog_clock \\\n\ + sim:/%s/op_clock \\\n\ + sim:/%s/in_* \\\n\ + sim:/%s/out_* \n", circuit_top_tb_name, + circuit_top_tb_name, + circuit_top_tb_name, + circuit_top_tb_name); fprintf(fp, "}\n"); @@ -418,7 +430,13 @@ void dump_verilog_modelsim_proc_auto_preconf_script(char* modelsim_proc_filename fprintf(fp, " \n"); fprintf(fp, "proc add_waves {} {\n"); - fprintf(fp, " add wave -position insertpoint sim:/%s/*\n", circuit_top_tb_name); + fprintf(fp, " add wave -position insertpoint sim:/%s/prog_clock \\\n\ + sim:/%s/op_clock \\\n\ + sim:/%s/in_* \\\n\ + sim:/%s/out_*\n", circuit_top_tb_name, + circuit_top_tb_name, + circuit_top_tb_name, + circuit_top_tb_name); fprintf(fp, "}\n"); @@ -656,9 +674,8 @@ void dump_verilog_modelsim_top_auto_preconf_script(char* modelsim_top_auto_scrip fprintf(fp, "\n"); fprintf(fp, "#in ms\n"); - fprintf(fp, "set simtime %.4g\n", sim_time); - fprintf(fp, "set unit %s\n", - sim_time_unit); + fprintf(fp, "set simtime 150\n"); + fprintf(fp, "set unit us\n"); fprintf(fp, "\n"); fprintf(fp, "#Path were both tcl script are located\n"); diff --git a/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_top_netlist.c b/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_top_netlist.c index 78c56f6b5..2ad472087 100644 --- a/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_top_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_top_netlist.c @@ -1640,9 +1640,9 @@ void dump_verilog_top_testbench_ports(FILE* fp, assert((VPACK_INPAD == logical_block[iblock].type)||(VPACK_OUTPAD == logical_block[iblock].type)); fprintf(fp, "//----- Blif Benchmark inout %s is mapped to FPGA IOPAD %s[%d] -----\n", logical_block[iblock].name, gio_inout_prefix, iopad_idx); - fprintf(fp, "wire %s_%s_%d_;\n", + fprintf(fp, "wire in_%s_%s_%d_;\n", logical_block[iblock].name, gio_inout_prefix, iopad_idx); - fprintf(fp, "assign %s_%s_%d_ = %s%s[%d];\n", + fprintf(fp, "assign in_%s_%s_%d_ = %s%s[%d];\n", logical_block[iblock].name, gio_inout_prefix, iopad_idx, gio_inout_prefix, iopad_verilog_model->prefix, iopad_idx); }