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Big chunk added on the routing part of the explicit mapping

This commit is contained in:
Baudouin Chauviere 2019-07-02 14:12:42 -06:00
parent 8f5ad2eb67
commit b08513d902
12 changed files with 222 additions and 121 deletions
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4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.c
View File

@ -354,6 +354,7 @@ void dump_verilog_autocheck_top_testbench(t_sram_orgz_info* cur_sram_orgz_info,
t_spice verilog) {
FILE* fp = NULL;
char* title = my_strcat("FPGA Verilog Testbench for Top-level netlist of Design: ", circuit_name);
bool is_explicit_mapping = fpga_verilog_opts.dump_explicit_verilog;
/* Check if the path exists*/
fp = fopen(top_netlist_name,"w");
@ -379,7 +380,8 @@ void dump_verilog_autocheck_top_testbench(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_top_auto_testbench_ports(fp, cur_sram_orgz_info, circuit_name, fpga_verilog_opts);
/* Call defined top-level module */
dump_verilog_top_testbench_call_top_module(cur_sram_orgz_info, fp, circuit_name);
dump_verilog_top_testbench_call_top_module(cur_sram_orgz_info, fp,
circuit_name, is_explicit_mapping);
/* Call defined benchmark */
dump_verilog_top_auto_testbench_call_benchmark(fp, circuit_name);

73
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
View File

@ -361,7 +361,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
fprintf(fp, "module %s ( \n", subckt_name);
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
@ -406,7 +406,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
0,
temp_conf_bits_msb - 1,
VERILOG_PORT_INPUT); // Should be modified to be VERILOG_PORT_INPUT
VERILOG_PORT_INPUT, is_explicit_mapping); // Should be modified to be VERILOG_PORT_INPUT
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -430,7 +430,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
fprintf(fp, " %s (", gen_verilog_one_phy_block_instance_name(phy_block_type, iz));
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
/* Print all the pins */
@ -464,7 +464,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
fprintf(fp, "//---- SRAM ----\n");
dump_verilog_sram_local_ports(fp, cur_sram_orgz_info,
temp_conf_bits_lsb, temp_conf_bits_msb - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
}
/* Dump ports only visible during formal verification*/
@ -475,7 +475,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
temp_conf_bits_lsb,
temp_conf_bits_msb - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -592,7 +592,8 @@ void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info,
static
void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
int ix, int iy, int border_side) {
int ix, int iy, int border_side,
bool is_explicit_mapping) {
char* subckt_name = NULL;
if (NULL == fp) {
@ -616,7 +617,7 @@ void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "(");
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
@ -648,7 +649,7 @@ void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_sram_local_ports(fp, cur_sram_orgz_info,
cur_sram_orgz_info->grid_conf_bits_lsb[ix][iy],
cur_sram_orgz_info->grid_conf_bits_msb[ix][iy] - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
}
/* Dump ports only visible during formal verification*/
@ -660,7 +661,7 @@ void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_sram_orgz_info->grid_conf_bits_lsb[ix][iy],
cur_sram_orgz_info->grid_conf_bits_msb[ix][iy] - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -676,7 +677,8 @@ void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info,
*/
static
void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp) {
FILE* fp,
bool is_explicit_mapping) {
int ix, iy;
if (NULL == fp) {
@ -692,7 +694,8 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info,
continue;
}
assert(IO_TYPE != grid[ix][iy].type);
dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, ix, iy, -1);
dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp,
ix, iy, -1, is_explicit_mapping);
}
}
@ -705,7 +708,8 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info,
continue;
}
assert(IO_TYPE == grid[ix][iy].type);
dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, ix, iy, 0);
dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp,
ix, iy, 0, is_explicit_mapping);
}
/* RIGHT side */
ix = nx + 1;
@ -715,7 +719,8 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info,
continue;
}
assert(IO_TYPE == grid[ix][iy].type);
dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, ix, iy, 1);
dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp,
ix, iy, 1, is_explicit_mapping);
}
/* BOTTOM side */
@ -726,7 +731,8 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info,
continue;
}
assert(IO_TYPE == grid[ix][iy].type);
dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, ix, iy, 2);
dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp,
ix, iy, 2, is_explicit_mapping);
}
/* LEFT side */
ix = 0;
@ -736,7 +742,8 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info,
continue;
}
assert(IO_TYPE == grid[ix][iy].type);
dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, ix, iy, 3);
dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, ix,
iy, 3, is_explicit_mapping);
}
@ -775,7 +782,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
@ -821,7 +828,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz
dump_verilog_sram_local_ports(fp, cur_sram_orgz_info,
rr_sb.get_sb_conf_bits_lsb(),
rr_sb.get_sb_conf_bits_msb(),
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
}
/* Dump ports only visible during formal verification*/
@ -833,7 +840,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
rr_sb.get_sb_conf_bits_lsb(),
rr_sb.get_sb_conf_bits_msb(),
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -901,7 +908,7 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_
fprintf(fp, "(");
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
@ -949,7 +956,7 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_
dump_verilog_sram_local_ports(fp, cur_sram_orgz_info,
rr_gsb.get_cb_conf_bits_lsb(cb_type),
rr_gsb.get_cb_conf_bits_msb(cb_type),
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
}
/* Dump ports only visible during formal verification*/
if (0 < rr_gsb.get_cb_num_conf_bits(cb_type)) {
@ -959,7 +966,7 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
rr_gsb.get_cb_conf_bits_lsb(cb_type),
rr_gsb.get_cb_conf_bits_msb(cb_type),
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -1019,7 +1026,9 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or
static
void dump_compact_verilog_defined_one_channel(FILE* fp,
int x, int y,
const RRChan& rr_chan, size_t subckt_id) {
const RRChan& rr_chan,
size_t subckt_id,
bool is_explicit_mapping) {
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__);
exit(1);
@ -1053,7 +1062,7 @@ void dump_compact_verilog_defined_one_channel(FILE* fp,
fprintf(fp, "(");
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
@ -1140,7 +1149,8 @@ void dump_compact_verilog_defined_one_channel(FILE* fp,
/* Call the sub-circuits for channels : Channel X and Channel Y*/
static
void dump_compact_verilog_defined_channels(FILE* fp) {
void dump_compact_verilog_defined_channels(FILE* fp,
bool is_explicit_mapping) {
int ix, iy;
if (NULL == fp) {
@ -1153,7 +1163,8 @@ void dump_compact_verilog_defined_channels(FILE* fp) {
for (ix = 1; ix < (nx + 1); ix++) {
dump_compact_verilog_defined_one_channel(fp, ix, iy,
device_rr_chan.get_module_with_coordinator(CHANX, ix, iy),
device_rr_chan.get_module_id(CHANX, ix, iy));
device_rr_chan.get_module_id(CHANX, ix, iy),
is_explicit_mapping);
}
}
@ -1162,7 +1173,8 @@ void dump_compact_verilog_defined_channels(FILE* fp) {
for (iy = 1; iy < (ny + 1); iy++) {
dump_compact_verilog_defined_one_channel(fp, ix, iy,
device_rr_chan.get_module_with_coordinator(CHANY, ix, iy),
device_rr_chan.get_module_id(CHANY, ix, iy));
device_rr_chan.get_module_id(CHANY, ix, iy),
is_explicit_mapping);
}
}
@ -1234,15 +1246,16 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info,
my_free(temp_include_file_path);
/* Print all global wires*/
dump_verilog_top_netlist_ports(cur_sram_orgz_info, fp, num_clock, circuit_name, verilog);
dump_verilog_top_netlist_ports(cur_sram_orgz_info, fp, num_clock,
circuit_name, verilog, is_explicit_mapping);
dump_verilog_top_netlist_internal_wires(cur_sram_orgz_info, fp);
/* Quote Routing structures: Channels */
if (TRUE == compact_routing_hierarchy ) {
dump_compact_verilog_defined_channels(fp);
dump_compact_verilog_defined_channels(fp, is_explicit_mapping);
} else {
dump_verilog_defined_channels(fp, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices);
dump_verilog_defined_channels(fp, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, is_explicit_mapping);
}
/* Quote Routing structures: Switch Boxes */
@ -1260,7 +1273,7 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info,
}
/* Quote defined Logic blocks subckts (Grids) */
dump_compact_verilog_defined_grids(cur_sram_orgz_info, fp);
dump_compact_verilog_defined_grids(cur_sram_orgz_info, fp, is_explicit_mapping);
/* Apply CLB to CLB direct connections */
dump_verilog_clb2clb_directs(fp, num_clb2clb_directs, clb2clb_direct);

22
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
View File

@ -1733,7 +1733,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
*/
fprintf(fp, "\n");
/* dump global ports */
if(0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
if(0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
/* Simplify the port prefix, make SPICE netlist readable */
@ -1772,7 +1772,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
stamped_sram_cnt,
stamped_sram_cnt + num_conf_bits - 1,
VERILOG_PORT_INPUT);
VERILOG_PORT_INPUT, false);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -1819,7 +1819,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
/* dump global ports */
/* If the child node is a primitive, we only dump global ports belonging to this primitive */
if (NULL == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
} else {
@ -1863,7 +1863,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_sram_local_ports(fp, cur_sram_orgz_info,
stamped_sram_cnt,
stamped_sram_cnt + child_pb_num_conf_bits - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
}
/* Dump ports only visible during formal verification*/
if (0 < child_pb_num_conf_bits) {
@ -1873,7 +1873,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
stamped_sram_cnt,
stamped_sram_cnt + child_pb_num_conf_bits - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, false);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -2552,7 +2552,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "module %s ( \n", gen_verilog_one_grid_module_name(ix, iy));
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
@ -2596,7 +2596,8 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_num_mem_bit,
get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info) - 1,
VERILOG_PORT_INPUT);
VERILOG_PORT_INPUT,
false);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -2624,7 +2625,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, " %s (", gen_verilog_one_block_instance_name(ix, iy, iz));
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
/* Print all the pins */
@ -2659,7 +2660,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "//---- SRAM ----\n");
dump_verilog_sram_local_ports(fp, cur_sram_orgz_info,
temp_conf_bits_lsb, temp_conf_bits_msb - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
}
/* Dump ports only visible during formal verification*/
if (0 < (temp_conf_bits_msb - 1 - temp_conf_bits_lsb)) {
@ -2669,7 +2670,8 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
temp_conf_bits_lsb,
temp_conf_bits_msb - 1,
VERILOG_PORT_INPUT);
VERILOG_PORT_INPUT,
is_explicit_mapping);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}

4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c
View File

@ -173,7 +173,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_num_sram,
cur_num_sram + num_conf_bits - 1,
VERILOG_PORT_INPUT);
VERILOG_PORT_INPUT, false);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -560,7 +560,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_num_sram,
cur_num_sram + num_conf_bits - 1,
VERILOG_PORT_INPUT);
VERILOG_PORT_INPUT, false);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}

119
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
View File

@ -44,7 +44,8 @@ static
void dump_verilog_routing_chan_subckt(char* verilog_dir,
char* subckt_dir,
size_t rr_chan_subckt_id,
const RRChan& rr_chan) {
const RRChan& rr_chan,
bool is_explicit_mapping) {
FILE* fp = NULL;
char* fname = NULL;
@ -78,7 +79,7 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir,
gen_verilog_one_routing_channel_module_name(rr_chan.get_type(), rr_chan_subckt_id, -1));
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) {
fprintf(fp, ",\n");
}
/* Inputs and outputs,
@ -170,7 +171,8 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices,
t_rr_indexed_data* LL_rr_indexed_data,
int num_segment) {
int num_segment,
bool is_explicit_mapping) {
int itrack, iseg, cost_index;
int chan_width = 0;
t_rr_node** chan_rr_nodes = NULL;
@ -215,7 +217,7 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir,
gen_verilog_one_routing_channel_module_name(chan_type, x, y));
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) {
fprintf(fp, ",\n");
}
/* Inputs and outputs,
@ -355,9 +357,10 @@ void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type,
/* fprintf(fp, "grid_%d__%d__pin_%d__%d__%d_ ", x, y, height, side, pin_index); */
if (TRUE == dump_port_type) {
fprintf(fp, "%s ", verilog_port_type);
is_explicit_mapping = false; /* Both cannot be true at the same time */
}
if (true == is_explicit_mapping) {
fprintf(fp, ".out(");
fprintf(fp, ".%s(", gen_verilog_grid_one_pin_name(x, y, height, side, pin_index, TRUE));
}
fprintf(fp, "%s", gen_verilog_grid_one_pin_name(x, y, height, side, pin_index, TRUE));
if (true == is_explicit_mapping) {
@ -562,7 +565,7 @@ void dump_verilog_unique_switch_box_short_interc(FILE* fp,
drive_rr_node->ptc_num,
rr_sb.get_opin_node_grid_side(drive_rr_node),
grid_x, grid_y,
FALSE, is_explicit_mapping); /* Do not dump the direction of the port! */
FALSE, false); /* Do not dump the direction of the port! */
break;
case CHANX:
case CHANY:
@ -1025,7 +1028,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
verilog_model->prefix, mux_size, verilog_model->cnt, input_cnt);
dump_verilog_grid_side_pin_with_given_index(fp, IPIN, drive_rr_nodes[inode]->ptc_num,
rr_sb.get_opin_node_grid_side(drive_rr_nodes[inode]),
grid_x, grid_y, FALSE, is_explicit_mapping);
grid_x, grid_y, FALSE, false);
fprintf(fp, ";\n");
input_cnt++;
break;
@ -1741,11 +1744,22 @@ void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp,
fprintf(fp, " ");
if (TRUE == dump_port_type) {
fprintf(fp, "output ");
is_explicit_mapping = false; /* Both cannot be true together */
}
fprintf(fp, "%s,\n",
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack),
port_coordinator.get_x(), port_coordinator.get_y(), itrack,
rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)));
}
fprintf(fp, "%s",
gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack),
port_coordinator.get_x(), port_coordinator.get_y(), itrack,
rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)));
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ",\n");
break;
case IN_PORT:
/* if this is not the specified side, we only consider input ports */
@ -1756,10 +1770,20 @@ void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp,
if (TRUE == dump_port_type) {
fprintf(fp, "input ");
}
fprintf(fp, "%s,\n",
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack),
port_coordinator.get_x(), port_coordinator.get_y(), itrack,
rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)));
}
fprintf(fp, "%s",
gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack),
port_coordinator.get_x(), port_coordinator.get_y(), itrack,
rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)));
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ",\n");
break;
default:
vpr_printf(TIO_MESSAGE_ERROR,
@ -1870,7 +1894,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr
/* Print the definition of subckt*/
fprintf(fp, "module %s ( \n", rr_sb.gen_sb_verilog_side_module_name(side, seg_id));
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) {
fprintf(fp, ",\n");
}
@ -1902,7 +1926,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_num_sram,
esti_sram_cnt - 1,
VERILOG_PORT_INPUT);
VERILOG_PORT_INPUT, is_explicit_mapping);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -2005,7 +2029,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
/* Print the definition of subckt*/
fprintf(fp, "module %s ( \n", rr_gsb.gen_sb_verilog_module_name());
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) {
fprintf(fp, ",\n");
}
@ -2076,7 +2100,8 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
rr_gsb.get_sb_conf_bits_lsb(),
rr_gsb.get_sb_conf_bits_msb(),
VERILOG_PORT_INPUT);
VERILOG_PORT_INPUT,
is_explicit_mapping);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -2122,7 +2147,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
rr_gsb.gen_sb_verilog_side_module_name(side_manager.get_side(), seg_ids[iseg]),
rr_gsb.gen_sb_verilog_side_instance_name(side_manager.get_side(), seg_ids[iseg]));
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
@ -2142,7 +2167,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
dump_verilog_sram_local_ports(fp, cur_sram_orgz_info,
cur_sram_lsb,
cur_sram_msb,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
/* Dump ports only visible during formal verification*/
if (0 < side_num_conf_bits) {
@ -2152,7 +2177,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_sram_lsb,
cur_sram_msb,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -2249,7 +2274,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or
/* Print the definition of subckt*/
fprintf(fp, "module %s ( \n", rr_gsb.gen_sb_verilog_module_name());
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
@ -2316,7 +2341,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
rr_gsb.get_sb_conf_bits_lsb(),
rr_gsb.get_sb_conf_bits_msb(),
VERILOG_PORT_OUTPUT);
VERILOG_PORT_OUTPUT, is_explicit_mapping);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -2454,7 +2479,7 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info
/* Print the definition of subckt*/
fprintf(fp, "module %s ( \n", gen_verilog_one_sb_module_name(cur_sb_info));
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
@ -2517,7 +2542,7 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_sb_info->conf_bits_lsb,
cur_sb_info->conf_bits_msb - 1,
VERILOG_PORT_INPUT);
VERILOG_PORT_INPUT, is_explicit_mapping);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -2679,8 +2704,7 @@ int count_verilog_connection_box_one_side_reserved_conf_bits(t_sram_orgz_info* c
static
void dump_verilog_connection_box_short_interc(FILE* fp,
const RRGSB& rr_gsb, t_rr_type cb_type,
t_rr_node* src_rr_node,
bool is_explicit_mapping) {
t_rr_node* src_rr_node) {
t_rr_node* drive_rr_node = NULL;
int iedge, check_flag;
int xlow, ylow, height, index;
@ -2734,7 +2758,7 @@ void dump_verilog_connection_box_short_interc(FILE* fp,
rr_gsb.get_ipin_node(side, index)->ptc_num,
rr_gsb.get_ipin_node_grid_side(side, index),
xlow, ylow, /* Coordinator of Grid */
FALSE, is_explicit_mapping); /* Do not specify the direction of this pin */
FALSE, false); /* Do not specify the direction of this pin */
/* End */
fprintf(fp, ";\n");
@ -2811,7 +2835,7 @@ void dump_verilog_connection_box_short_interc(FILE* fp,
cur_cb_info->ipin_rr_node[side][index]->ptc_num,
cur_cb_info->ipin_rr_node_grid_side[side][index],
xlow, ylow, /* Coordinator of Grid */
FALSE, is_explicit_mapping); /* Do not specify the direction of this pin */
FALSE, false); /* Do not specify the direction of this pin */
/* End */
fprintf(fp, ";\n");
@ -2942,8 +2966,15 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
}
/* connect to input bus*/
fprintf(fp, "%s_size%d_%d_inbus,",
if (true == is_explicit_mapping) {
fprintf(fp, ".in(");
}
fprintf(fp, "%s_size%d_%d_inbus",
verilog_model->prefix, mux_size, verilog_model->cnt);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
/* output port*/
xlow = src_rr_node->xlow;
@ -2954,11 +2985,17 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
rr_gsb.get_node_side_and_index(src_rr_node, OUT_PORT, &side, &index);
/* We need to be sure that drive_rr_node is part of the CB */
assert((-1 != index)&&(NUM_SIDES != side));
if (true == is_explicit_mapping) {
fprintf(fp, ".out(");
}
dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an output of a connection box */
rr_gsb.get_ipin_node(side, index)->ptc_num,
rr_gsb.get_ipin_node_grid_side(side, index),
xlow, ylow, /* Coordinator of Grid */
FALSE, is_explicit_mapping); /* Do not specify the direction of port */
FALSE, false); /* Do not specify the direction of port */
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
/* Different design technology requires different configuration bus! */
@ -3162,7 +3199,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
cur_num_sram,
cur_num_sram + num_mux_conf_bits - 1);
fprintf(fp, "`endif\n");
fprintf(fp, "is_explicit_mappingf\n");
/* Call the MUX SPICE model */
@ -3195,11 +3232,17 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
get_rr_node_side_and_index_in_cb_info(src_rr_node, (*cur_cb_info), OUT_PORT, &side, &index);
/* We need to be sure that drive_rr_node is part of the CB */
assert((-1 != index)&&(-1 != side));
if (true == is_explicit_mapping) {
fprintf(fp, ".out(");
}
dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an output of a connection box */
cur_cb_info->ipin_rr_node[side][index]->ptc_num,
cur_cb_info->ipin_rr_node_grid_side[side][index],
xlow, ylow, /* Coordinator of Grid */
FALSE, is_explicit_mapping); /* Do not specify the direction of port */
FALSE, false); /* Do not specify the direction of port */
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
/* Different design technology requires different configuration bus! */
@ -3305,7 +3348,7 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
if (1 == src_rr_node->fan_in) {
/* Print a direct connection*/
dump_verilog_connection_box_short_interc(fp, rr_gsb, cb_type, src_rr_node, is_explicit_mapping);
dump_verilog_connection_box_short_interc(fp, rr_gsb, cb_type, src_rr_node);
} else if (1 < src_rr_node->fan_in) {
/* Print the multiplexer, fan_in >= 2 */
dump_verilog_connection_box_mux(cur_sram_orgz_info, fp, rr_gsb, cb_type,
@ -3502,7 +3545,7 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra
fprintf(fp, "%s ", rr_gsb.gen_cb_verilog_module_name(cb_type));
fprintf(fp, "(\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) {
fprintf(fp, ",\n");
}
/* Print the ports of channels*/
@ -3525,7 +3568,7 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra
rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode),
rr_gsb.get_ipin_node(cb_ipin_side, inode)->xlow,
rr_gsb.get_ipin_node(cb_ipin_side, inode)->ylow,
TRUE, is_explicit_mapping);
TRUE, false);
}
}
@ -3554,7 +3597,7 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
rr_gsb.get_cb_conf_bits_lsb(cb_type),
rr_gsb.get_cb_conf_bits_msb(cb_type),
VERILOG_PORT_INPUT);
VERILOG_PORT_INPUT, false);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -3704,7 +3747,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_
fprintf(fp, "(\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) {
fprintf(fp, ",\n");
}
/* Print the ports of channels*/
@ -3776,7 +3819,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_cb_info->conf_bits_lsb,
cur_cb_info->conf_bits_msb - 1,
VERILOG_PORT_INPUT);
VERILOG_PORT_INPUT, is_explicit_mapping);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -3876,13 +3919,13 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
/* X - channels [1...nx][0..ny]*/
for (size_t ichan = 0; ichan < device_rr_chan.get_num_modules(CHANX); ++ichan) {
dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir,
ichan, device_rr_chan.get_module(CHANX, ichan));
ichan, device_rr_chan.get_module(CHANX, ichan), explicit_port_mapping);
}
/* Y - channels [1...ny][0..nx]*/
vpr_printf(TIO_MESSAGE_INFO, "Writing Y-direction Channels...\n");
for (size_t ichan = 0; ichan < device_rr_chan.get_num_modules(CHANY); ++ichan) {
dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir,
ichan, device_rr_chan.get_module(CHANY, ichan));
ichan, device_rr_chan.get_module(CHANY, ichan), explicit_port_mapping);
}
} else {
/* Output the full array of routing channels */
@ -3891,7 +3934,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
for (int ix = 1; ix < (nx + 1); ix++) {
dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, ix, iy, CHANX,
LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, LL_rr_indexed_data,
arch.num_segments);
arch.num_segments, explicit_port_mapping);
}
}
/* Y - channels [1...ny][0..nx]*/
@ -3900,7 +3943,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
for (int iy = 1; iy < (ny + 1); iy++) {
dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, ix, iy, CHANY,
LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, LL_rr_indexed_data,
arch.num_segments);
arch.num_segments, explicit_port_mapping);
}
}
}

44
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c
View File

@ -131,7 +131,7 @@ void dump_verilog_top_netlist_memory_bank_internal_wires(t_sram_orgz_info* cur_s
fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag);
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
0, get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info) - 1,
VERILOG_PORT_WIRE);
VERILOG_PORT_WIRE, false);
fprintf(fp, ";\n");
fprintf(fp, "`endif\n");
break;
@ -217,7 +217,7 @@ void dump_verilog_top_netlist_scan_chain_internal_wires(t_sram_orgz_info* cur_sr
fprintf(fp, " ");
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
0, num_scffs - 1,
VERILOG_PORT_WIRE);
VERILOG_PORT_WIRE, false);
fprintf(fp, ";\n");
fprintf(fp, "`endif\n");
@ -249,7 +249,8 @@ void dump_verilog_top_netlist_scan_chain_internal_wires(t_sram_orgz_info* cur_sr
/* Dump ports for the top-level module in Verilog netlist */
void dump_verilog_top_module_ports(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
enum e_dump_verilog_port_type dump_port_type) {
enum e_dump_verilog_port_type dump_port_type,
bool is_explicit_mapping) {
char* port_name = NULL;
char split_sign;
enum e_dump_verilog_port_type actual_dump_port_type;
@ -265,7 +266,7 @@ void dump_verilog_top_module_ports(t_sram_orgz_info* cur_sram_orgz_info,
}
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, dump_global_port_type)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, dump_global_port_type, is_explicit_mapping)) {
fprintf(fp, "%c\n", split_sign);
}
/* Inputs and outputs of I/O pads */
@ -317,7 +318,8 @@ void dump_verilog_top_netlist_ports(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
int num_clocks,
char* circuit_name,
t_spice verilog) {
t_spice verilog,
bool is_explicit_mapping) {
/*
int num_array_bl, num_array_wl;
int bl_decoder_size, wl_decoder_size;
@ -334,7 +336,8 @@ void dump_verilog_top_netlist_ports(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "module %s_top (\n", circuit_name);
fprintf(fp, "\n");
dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_INPUT);
dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_INPUT,
is_explicit_mapping);
fprintf(fp, ");\n");
@ -367,7 +370,8 @@ void dump_verilog_top_netlist_internal_wires(t_sram_orgz_info* cur_sram_orgz_inf
static
void dump_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
int ix, int iy) {
int ix, int iy,
bool is_explicit_mapping) {
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__);
exit(1);
@ -387,7 +391,7 @@ void dump_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "(");
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
@ -435,7 +439,8 @@ static
void dump_verilog_defined_one_channel(FILE* fp,
t_rr_type chan_type, int x, int y,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices) {
t_ivec*** LL_rr_node_indices,
bool is_explicit_mapping) {
int itrack;
int chan_width = 0;
t_rr_node** chan_rr_nodes = NULL;
@ -477,7 +482,7 @@ void dump_verilog_defined_one_channel(FILE* fp,
fprintf(fp, "(");
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports_explicit(fp, global_ports_head, FALSE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
@ -572,7 +577,8 @@ void dump_verilog_defined_one_channel(FILE* fp,
/* Call the sub-circuits for channels : Channel X and Channel Y*/
void dump_verilog_defined_channels(FILE* fp,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices) {
t_ivec*** LL_rr_node_indices,
bool is_explicit_mapping) {
int ix, iy;
if (NULL == fp) {
@ -584,7 +590,7 @@ void dump_verilog_defined_channels(FILE* fp,
for (iy = 0; iy < (ny + 1); iy++) {
for (ix = 1; ix < (nx + 1); ix++) {
dump_verilog_defined_one_channel(fp, CHANX, ix, iy,
LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices);
LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, is_explicit_mapping);
}
}
@ -592,7 +598,7 @@ void dump_verilog_defined_channels(FILE* fp,
for (ix = 0; ix < (nx + 1); ix++) {
for (iy = 1; iy < (ny + 1); iy++) {
dump_verilog_defined_one_channel(fp, CHANY, ix, iy,
LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices);
LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, is_explicit_mapping);
}
}
@ -638,7 +644,7 @@ void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_inf
fprintf(fp, "(");
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
@ -699,7 +705,7 @@ void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_inf
if (0 < (cur_cb_info.conf_bits_msb - cur_cb_info.conf_bits_lsb)) {
dump_verilog_sram_local_ports(fp, cur_sram_orgz_info,
cur_cb_info.conf_bits_lsb, cur_cb_info.conf_bits_msb - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
}
/* Dump ports only visible during formal verification*/
if (0 < (cur_cb_info.conf_bits_msb - 1 - cur_cb_info.conf_bits_lsb)) {
@ -709,7 +715,7 @@ void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_inf
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_cb_info.conf_bits_lsb,
cur_cb_info.conf_bits_msb - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -805,7 +811,7 @@ void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
@ -847,7 +853,7 @@ void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_sram_local_ports(fp, cur_sram_orgz_info,
cur_sb_info.conf_bits_lsb,
cur_sb_info.conf_bits_msb - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
}
/* Dump ports only visible during formal verification*/
@ -858,7 +864,7 @@ void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_sb_info.conf_bits_lsb,
cur_sb_info.conf_bits_msb - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}

9
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h
View File

@ -3,14 +3,16 @@ void dump_verilog_top_netlist_ports(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
int num_clocks,
char* circuit_name,
t_spice verilog);
t_spice verilog,
bool is_explicit_mapping);
void dump_verilog_top_netlist_internal_wires(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp);
void dump_verilog_defined_channels(FILE* fp,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices);
t_ivec*** LL_rr_node_indices,
bool is_explicit_mapping);
void dump_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp, bool is_explicit_mapping);
@ -26,7 +28,8 @@ void dump_verilog_configuration_circuits(t_sram_orgz_info* cur_sram_orgz_info,
void dump_verilog_top_module_ports(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
enum e_dump_verilog_port_type dump_port_type);
enum e_dump_verilog_port_type dump_port_type,
bool is_explicit_mapping);
void verilog_compact_generate_fake_xy_for_io_border_side(int border_side,
int* ix, int* iy) ;

7
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.c
View File

@ -312,7 +312,8 @@ void dump_verilog_top_testbench_ports(t_sram_orgz_info* cur_sram_orgz_info,
void dump_verilog_top_testbench_call_top_module(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
char* circuit_name) {
char* circuit_name,
bool is_explicit_mapping) {
/*
int iblock, iopad_idx;
*/
@ -322,7 +323,7 @@ void dump_verilog_top_testbench_call_top_module(t_sram_orgz_info* cur_sram_orgz_
fprintf(fp, "//------Call defined Top-level Verilog Module -----\n");
fprintf(fp, "%s_top U0 (\n", circuit_name);
dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_CONKT);
dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_CONKT, is_explicit_mapping);
fprintf(fp, ");\n");
return;
@ -1354,7 +1355,7 @@ void dump_verilog_top_testbench(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_top_testbench_ports(cur_sram_orgz_info, fp, circuit_name);
/* Call defined top-level module */
dump_verilog_top_testbench_call_top_module(cur_sram_orgz_info, fp, circuit_name);
dump_verilog_top_testbench_call_top_module(cur_sram_orgz_info, fp, circuit_name, false);
/* Add stimuli for reset, set, clock and iopad signals */
dump_verilog_top_testbench_stimuli(cur_sram_orgz_info, fp, verilog);

3
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.h
View File

@ -6,7 +6,8 @@ void dump_verilog_top_testbench_global_ports_stimuli(FILE* fp, t_llist* head);
void dump_verilog_top_testbench_call_top_module(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
char* circuit_name);
char* circuit_name,
bool is_explicit_mapping);
void dump_verilog_top_testbench_stimuli(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,

43
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c
View File

@ -945,7 +945,8 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp,
/* Dump all the global ports that are stored in the linked list */
int dump_verilog_global_ports(FILE* fp, t_llist* head,
boolean dump_port_type) {
boolean dump_port_type,
bool is_explicit_mapping) {
t_llist* temp = head;
t_spice_model_port* cur_global_port = NULL;
int dumped_port_cnt = 0;
@ -959,6 +960,10 @@ int dump_verilog_global_ports(FILE* fp, t_llist* head,
/* fprintf(fp, "//----- BEGIN Global ports -----\n"); */
while(NULL != temp) {
cur_global_port = (t_spice_model_port*)(temp->dptr);
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
cur_global_port->prefix);
}
if (TRUE == dump_port_type) {
fprintf(fp, "%s [0:%d] %s",
verilog_convert_port_type_to_string(cur_global_port->type),
@ -969,7 +974,9 @@ int dump_verilog_global_ports(FILE* fp, t_llist* head,
cur_global_port->prefix,
cur_global_port->size - 1);
}
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
/* if this is the tail, we do not dump a comma */
if (NULL != temp->next) {
fprintf(fp, ", //---- global port \n");
@ -1357,7 +1364,8 @@ void dump_verilog_sram_outports(FILE* fp,
void dump_verilog_formal_verification_sram_ports(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
int sram_lsb, int sram_msb,
enum e_dump_verilog_port_type dump_port_type) {
enum e_dump_verilog_port_type dump_port_type,
bool is_explicit_mapping) {
t_spice_model* mem_model = NULL;
char* port_name = NULL;
char* port_full_name = NULL;
@ -1394,8 +1402,14 @@ void dump_verilog_formal_verification_sram_ports(FILE* fp,
/*Malloc and generate the full name of port */
port_full_name = (char*)my_malloc(sizeof(char)*(strlen(mem_model->prefix) + strlen(port_name) + 1 + 1));
sprintf(port_full_name, "%s_%s", mem_model->prefix, port_name);
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
port_full_name);
}
dump_verilog_generic_port(fp, dump_port_type, port_full_name, sram_lsb, sram_msb);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
/* Free */
/* Local variables such as port1_name and port2 name are automatically freed */
@ -1508,7 +1522,7 @@ void dump_verilog_formal_verification_sram_ports_wiring(FILE* fp,
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
sram_lsb, sram_msb,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, false);
fprintf(fp, ";\n");
return;
@ -1530,7 +1544,7 @@ void dump_verilog_formal_verification_mux_sram_ports_wiring(FILE* fp,
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
sram_lsb, sram_msb,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, false);
fprintf(fp, ";\n");
return;
@ -1540,7 +1554,8 @@ void dump_verilog_formal_verification_mux_sram_ports_wiring(FILE* fp,
void dump_verilog_sram_local_ports(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
int sram_lsb, int sram_msb,
enum e_dump_verilog_port_type dump_port_type) {
enum e_dump_verilog_port_type dump_port_type,
bool is_explicit_mapping) {
/* Need to dump inverted BL/WL if needed */
int num_blb_ports, num_wlb_ports;
t_spice_model_port** blb_port = NULL;
@ -1578,14 +1593,26 @@ void dump_verilog_sram_local_ports(FILE* fp,
break;
case SPICE_SRAM_SCAN_CHAIN:
/* Dump the first port: SRAM_out of CMOS MUX or BL of RRAM MUX */
if (true == is_explicit_mapping) {
fprintf(fp, ".scff_scff_head(");
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
sram_lsb, sram_lsb,
-1, dump_port_type);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ",\n");
/* Dump the first port: SRAM_outb of CMOS MUX or WL of RRAM MUX */
if (true == is_explicit_mapping) {
fprintf(fp, ".scff_scff_tail(");
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
sram_msb, sram_msb,
0, dump_port_type);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
break;
default:
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization !\n",
@ -2582,7 +2609,7 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m
if (TRUE == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ",\n");
fprintf(fp, ", ");
if (TRUE == is_explicit_mapping) {
fprintf(fp, ".sram_inv(");
}

9
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h
View File

@ -76,7 +76,8 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp,
boolean require_explicit_port_map);
int dump_verilog_global_ports(FILE* fp, t_llist* head,
boolean dump_port_type);
boolean dump_port_type,
bool is_explicit_mapping);
int dump_verilog_global_ports_explicit(FILE* fp, t_llist* head,
boolean dump_port_type);
@ -115,7 +116,8 @@ void dump_verilog_sram_outports(FILE* fp,
void dump_verilog_formal_verification_sram_ports(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
int sram_lsb, int sram_msb,
enum e_dump_verilog_port_type dump_port_type);
enum e_dump_verilog_port_type dump_port_type,
bool is_explicit_mapping);
void dump_verilog_sram_one_port(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
@ -126,7 +128,8 @@ void dump_verilog_sram_one_port(FILE* fp,
void dump_verilog_sram_local_ports(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
int sram_lsb, int sram_msb,
enum e_dump_verilog_port_type dump_port_type);
enum e_dump_verilog_port_type dump_port_type,
bool is_explicit_mapping);
void dump_verilog_sram_ports(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info,
int sram_lsb, int sram_msb,

6
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_verification_top_netlist.c
View File

@ -187,7 +187,7 @@ void dump_verilog_formal_verfication_top_netlist_call_top_module(t_sram_orgz_inf
circuit_name,
formal_verification_top_module_uut_name);
dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_CONKT);
dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_CONKT, false);
fprintf(fp, ");\n");
return;
@ -338,14 +338,14 @@ void dump_verilog_formal_verification_top_netlist_config_bitstream(t_sram_orgz_i
case SPICE_SRAM_SCAN_CHAIN:
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_conf_bit->index, cur_conf_bit->index,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, false);
fprintf(fp, " = 1'b%d",
cur_conf_bit->sram_bit->val);
break;
case SPICE_SRAM_MEMORY_BANK:
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_conf_bit->bl->addr, cur_conf_bit->bl->addr,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, false);
fprintf(fp, " = 1'b%d",
cur_conf_bit->bl->val);
break;