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add explicit port mapping for inverters of memory decoders

This commit is contained in:
tangxifan 2019-06-10 17:36:14 -06:00
parent 8e3ad675e0
commit 1776ae3ec8
9 changed files with 90 additions and 20 deletions
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4
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c
View File

@ -456,7 +456,7 @@ void config_spice_model_input_output_buffers_pass_gate(int num_spice_models,
* BECAUSE spice_model will be a local copy if it is not a pointer. And it will be set free when this function
* finishes. So the return pointers become invalid !
*/
t_spice_model_port** find_spice_model_ports(t_spice_model* spice_model,
t_spice_model_port** find_spice_model_ports(const t_spice_model* spice_model,
enum e_spice_model_port_type port_type,
int* port_num, boolean ignore_global_port) {
int iport, cur;
@ -3209,7 +3209,7 @@ boolean is_primitive_pb_type(t_pb_type* cur_pb_type) {
/* Recursively find all the global ports in the spice_model / sub spice_model
*/
void rec_stats_spice_model_global_ports(t_spice_model* cur_spice_model,
void rec_stats_spice_model_global_ports(const t_spice_model* cur_spice_model,
boolean recursive,
t_llist** spice_model_head) {
int iport;

4
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h
View File

@ -46,7 +46,7 @@ void config_one_spice_model_buffer(int num_spice_models,
void config_spice_model_input_output_buffers_pass_gate(int num_spice_models,
t_spice_model* spice_model);
t_spice_model_port** find_spice_model_ports(t_spice_model* spice_model,
t_spice_model_port** find_spice_model_ports(const t_spice_model* spice_model,
enum e_spice_model_port_type port_type,
int* port_num, boolean ignore_global_port);
@ -379,7 +379,7 @@ boolean check_subckt_file_exist_in_llist(t_llist* subckt_llist_head,
boolean is_primitive_pb_type(t_pb_type* cur_pb_type);
void rec_stats_spice_model_global_ports(t_spice_model* cur_spice_model,
void rec_stats_spice_model_global_ports(const t_spice_model* cur_spice_model,
boolean recursive,
t_llist** spice_model_head);

81
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c
View File

@ -31,8 +31,9 @@
#include "verilog_global.h"
#include "verilog_utils.h"
/***** Subroutines *****/
#include "verilog_decoder.h"
/***** Subroutines *****/
void dump_verilog_decoder_memory_bank_ports(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
enum e_dump_verilog_port_type dump_port_type) {
@ -343,6 +344,66 @@ void dump_verilog_scan_chain_config_module(FILE* fp,
return;
}
/** Output a inverter module for inverting a BL/WL line
*/
static
void dump_verilog_membank_one_inv_module(FILE* fp,
const t_spice_model* inv_spice_model,
const char* instance_tag,
const char* in_port_name,
const char* out_port_name,
int inv_index) {
/* A valid file handler */
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__);
exit(1);
}
assert(NULL != instance_tag);
assert(NULL != in_port_name);
assert(NULL != out_port_name);
/* Find the input port, output port, and sram port*/
int num_buf_input_port;
int num_buf_output_port;
t_spice_model_port** buf_input_port = find_spice_model_ports(inv_spice_model, SPICE_MODEL_PORT_INPUT, &num_buf_input_port, TRUE);
t_spice_model_port** buf_output_port = find_spice_model_ports(inv_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_buf_output_port, TRUE);
/* Instanciate an inverter module */
fprintf(fp, " %s %s_%s_%d (",
inv_spice_model->name, inv_spice_model->prefix,
instance_tag, inv_index);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, inv_spice_model, FALSE, FALSE, inv_spice_model->dump_explicit_port_map)) {
fprintf(fp, ",\n");
}
/* Dump explicit port map if required */
if ( TRUE == inv_spice_model->dump_explicit_port_map) {
fprintf(fp, ".%s(",
buf_input_port[0]->lib_name);
}
fprintf(fp, "%s[%d]",
in_port_name, inv_index);
if ( TRUE == inv_spice_model->dump_explicit_port_map) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
if ( TRUE == inv_spice_model->dump_explicit_port_map) {
fprintf(fp, ".%s(",
buf_output_port[0]->lib_name);
}
fprintf(fp, "%s[%d]",
out_port_name, inv_index);
if ( TRUE == inv_spice_model->dump_explicit_port_map) {
fprintf(fp, ")");
}
fprintf(fp, ");\n");
/* Free */
my_free(buf_input_port);
my_free(buf_output_port);
return;
}
/* For Memory-bank configuration organization:
* Dump the module of configuration module which connect configuration ports to SRAMs/SCFFs
*/
@ -487,11 +548,10 @@ void dump_verilog_membank_config_module(FILE* fp,
blb_inv_spice_model = blb_port[0]->inv_spice_model;
/* Make an inversion of the BL */
for (iinv = 0; iinv < num_array_bl; iinv++) {
fprintf(fp, " %s %s_blb_%d (%s[%d], %s[%d]);\n",
blb_inv_spice_model->name, blb_inv_spice_model->prefix,
iinv,
top_netlist_array_bl_port_name, iinv,
top_netlist_array_blb_port_name, iinv);
dump_verilog_membank_one_inv_module(fp, blb_inv_spice_model, "blb",
top_netlist_array_bl_port_name,
top_netlist_array_blb_port_name,
iinv);
}
}
if (1 == num_wlb_ports) {
@ -499,11 +559,10 @@ void dump_verilog_membank_config_module(FILE* fp,
wlb_inv_spice_model = wlb_port[0]->inv_spice_model;
/* Make an inversion of the WL */
for (iinv = 0; iinv < num_array_wl; iinv++) {
fprintf(fp, " %s %s_wlb_%d (%s[%d], %s[%d]);\n",
wlb_inv_spice_model->name, wlb_inv_spice_model->prefix,
iinv,
top_netlist_array_wl_port_name, iinv,
top_netlist_array_wlb_port_name, iinv);
dump_verilog_membank_one_inv_module(fp, wlb_inv_spice_model, "wlb",
top_netlist_array_wl_port_name,
top_netlist_array_wlb_port_name,
iinv);
}
}

4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.h
View File

@ -1,3 +1,5 @@
#ifndef VERILOG_DECODER_H
#define VERILOG_DECODER_H
void dump_verilog_decoder_memory_bank_ports(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
@ -6,3 +8,5 @@ void dump_verilog_decoder_memory_bank_ports(t_sram_orgz_info* cur_sram_orgz_info
void dump_verilog_config_peripherals(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir_path,
char* submodule_dir);
#endif

2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c
View File

@ -28,6 +28,8 @@
#include "verilog_global.h"
#include "verilog_utils.h"
#include "verilog_include_netlists.h"
static
void include_netlists_include_user_defined_verilog_netlists(FILE* fp,
t_spice spice) {

5
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.h
View File

@ -1,3 +1,8 @@
#ifndef VERILOG_INCLUDE_NETLISTS_H
#define VERILOG_INCLUDE_NETLISTS_H
void write_include_netlists (char* src_dir_formatted,
char* chomped_circuit_name,
t_spice spice);
#endif

2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c
View File

@ -1244,7 +1244,7 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp,
spice_model.lut_intermediate_buffer->spice_model_name,
nextlevel, out_idx); /* Given name*/
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.lut_intermediate_buffer->spice_model, FALSE, FALSE, TRUE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.lut_intermediate_buffer->spice_model, FALSE, FALSE, spice_model.lut_intermediate_buffer->spice_model->dump_explicit_port_map)) {
fprintf(fp, ",\n");
}
/* Dump explicit port map if required */

4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c
View File

@ -758,7 +758,7 @@ char* verilog_convert_port_type_to_string(enum e_spice_model_port_type port_type
* Return the number of ports that have been dumped
*/
int rec_dump_verilog_spice_model_lib_global_ports(FILE* fp,
t_spice_model* cur_spice_model,
const t_spice_model* cur_spice_model,
boolean dump_port_type,
boolean recursive,
boolean require_explicit_port_map) {
@ -851,7 +851,7 @@ int rec_dump_verilog_spice_model_lib_global_ports(FILE* fp,
* Return the number of ports that have been dumped
*/
int rec_dump_verilog_spice_model_global_ports(FILE* fp,
t_spice_model* cur_spice_model,
const t_spice_model* cur_spice_model,
boolean dump_port_type,
boolean recursive,
boolean require_explicit_port_map) {

4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h
View File

@ -64,13 +64,13 @@ char* format_verilog_node_prefix(char* verilog_node_prefix);
char* verilog_convert_port_type_to_string(enum e_spice_model_port_type port_type);
int rec_dump_verilog_spice_model_lib_global_ports(FILE* fp,
t_spice_model* cur_spice_model,
const t_spice_model* cur_spice_model,
boolean dump_port_type,
boolean recursive,
boolean require_explicit_port_map);
int rec_dump_verilog_spice_model_global_ports(FILE* fp,
t_spice_model* cur_spice_model,
const t_spice_model* cur_spice_model,
boolean dump_port_type,
boolean recursive,
boolean require_explicit_port_map);