Hot fix

2019-07-11 17:27:31 -06:00 · 2019-07-11 17:27:31 -06:00 · d0cd5a2bc1
parent 9c203ca4d2
commit d0cd5a2bc1
1 changed files with 2 additions and 2 deletions
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c
@ -902,8 +902,8 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp,
      /* Add explicit port mapping if required */
      if (TRUE == require_explicit_port_map ) {
        fprintf(fp, ".%s(",
-                /* cur_spice_model_port->lib_name); /* Old version*/
-                cur_spice_model_port->prefix);
+                 cur_spice_model_port->lib_name);
+                /*cur_spice_model_port->prefix);*/
      }
      fprintf(fp, "%s[0:%d]", 
            cur_spice_model_port->prefix,