From d0cd5a2bc108d6bb026f5cc95861a62be0eac5d2 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Thu, 11 Jul 2019 17:27:31 -0600 Subject: [PATCH] Hot fix --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index d2da736c1..eef883b00 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -902,8 +902,8 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, /* Add explicit port mapping if required */ if (TRUE == require_explicit_port_map ) { fprintf(fp, ".%s(", - /* cur_spice_model_port->lib_name); /* Old version*/ - cur_spice_model_port->prefix); + cur_spice_model_port->lib_name); + /*cur_spice_model_port->prefix);*/ } fprintf(fp, "%s[0:%d]", cur_spice_model_port->prefix,