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correction Null issue for the flat model

This commit is contained in:
Baudouin Chauviere 2019-05-28 14:15:24 -06:00
parent ffdcd4bb9c
commit 3da216f297
2 changed files with 9 additions and 2 deletions
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10
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c
View File

@ -1033,10 +1033,13 @@ void verilog_generate_sdc_disable_unused_sbs_muxs(FILE* fp) {
}
t_rr_node* cur_rr_node = rr_sb.get_chan_node(side_manager.get_side(), itrack);
for (int imux = 0 ; imux < cur_rr_node->fan_in; ++imux) {
if (1 == cur_rr_node->fan_in) {
continue;
}
if (imux == cur_rr_node->id_path) {
fprintf(fp, "#"); // comments out if the node is active
}
//if(cur_rr_node->name_mux == NULL) assert (NULL != cur_rr_node->name_mux);
//if(cur_rr_node->name_mux == NULL) assert (NULL != cur_rr_node->name_mux);
fprintf(fp, "set_disable_timing %s[%d]\n",
cur_rr_node->name_mux, imux);
}
@ -1070,10 +1073,13 @@ void verilog_generate_sdc_disable_unused_sbs_muxs(FILE* fp, int LL_nx, int LL_ny
if (OUT_PORT == cur_sb_info->chan_rr_node_direction[side][itrack]) {
cur_rr_node = cur_sb_info->chan_rr_node[side][itrack];
for (imux = 0 ; imux < cur_rr_node-> fan_in; imux++) {
if (1 == cur_rr_node->fan_in) {
continue;
}
if (imux == cur_rr_node->id_path) {
fprintf(fp, "#"); // comments out if the node is active
}
//if(cur_rr_node->name_mux == NULL) assert (NULL != cur_rr_node->name_mux);
//if(cur_rr_node->name_mux == NULL) assert (NULL != cur_rr_node->name_mux);
fprintf(fp, "set_disable_timing %s[%d]\n",
cur_rr_node->name_mux, imux);
}

1
vpr7_x2p/vpr/go_fpga_verilog.sh
View File

@ -34,6 +34,7 @@ set vpr_route_chan_width = 200
#make -j32
# Remove previous designs
rm -rf $verilog_output_dirpath/$verilog_output_dirname
rm -rf $verilog_output_dirpath/$verilog_output_dirname\_compact
# Run VPR
#valgrind