diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c
index 9785170b4..5b36b0b37 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c
@@ -1033,10 +1033,13 @@ void verilog_generate_sdc_disable_unused_sbs_muxs(FILE* fp) {
           }
           t_rr_node* cur_rr_node = rr_sb.get_chan_node(side_manager.get_side(), itrack);
           for (int imux = 0 ; imux < cur_rr_node->fan_in; ++imux) {
+            if (1 == cur_rr_node->fan_in) {
+              continue;
+            }
             if (imux == cur_rr_node->id_path) {
               fprintf(fp, "#"); // comments out if the node is active
             }
-//if(cur_rr_node->name_mux == NULL) assert (NULL != cur_rr_node->name_mux);
+            //if(cur_rr_node->name_mux == NULL) assert (NULL != cur_rr_node->name_mux);
             fprintf(fp, "set_disable_timing  %s[%d]\n", 
                     cur_rr_node->name_mux, imux);
           }
@@ -1070,10 +1073,13 @@ void verilog_generate_sdc_disable_unused_sbs_muxs(FILE* fp, int LL_nx, int LL_ny
           if (OUT_PORT == cur_sb_info->chan_rr_node_direction[side][itrack]) {
             cur_rr_node = cur_sb_info->chan_rr_node[side][itrack];
             for (imux = 0 ; imux < cur_rr_node-> fan_in; imux++) {
+              if (1 == cur_rr_node->fan_in) {
+                continue;
+              }
               if (imux == cur_rr_node->id_path) {
                 fprintf(fp, "#"); // comments out if the node is active
               }
-//if(cur_rr_node->name_mux == NULL) assert (NULL != cur_rr_node->name_mux);
+              //if(cur_rr_node->name_mux == NULL) assert (NULL != cur_rr_node->name_mux);
               fprintf(fp, "set_disable_timing  %s[%d]\n", 
                       cur_rr_node->name_mux, imux);
             }
diff --git a/vpr7_x2p/vpr/go_fpga_verilog.sh b/vpr7_x2p/vpr/go_fpga_verilog.sh
index 969ebceb3..cd1955b62 100755
--- a/vpr7_x2p/vpr/go_fpga_verilog.sh
+++ b/vpr7_x2p/vpr/go_fpga_verilog.sh
@@ -34,6 +34,7 @@ set vpr_route_chan_width = 200
 #make -j32
 # Remove previous designs
 rm -rf $verilog_output_dirpath/$verilog_output_dirname
+rm -rf $verilog_output_dirpath/$verilog_output_dirname\_compact
 
 # Run VPR  
 #valgrind