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fixing bugs in the SDC generator and report_timing

This commit is contained in:
tangxifan 2019-06-26 18:09:09 -06:00
parent 0fe54d87d5
commit 711e369fe7
3 changed files with 62 additions and 45 deletions
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8
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c
View File

@ -405,7 +405,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
t_pb_graph_node* prim_pb_graph_node,
int index,
t_spice_model* verilog_model) {
int i, ipin;
int i;
int lut_size = 0;
int num_input_port = 0;
t_spice_model_port** input_ports = NULL;
@ -418,12 +418,6 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
int num_mode_sram = 0;
t_spice_model_port* lut_sram_port = NULL;
int num_pb_type_input_port = 0;
t_port** pb_type_input_ports = NULL;
int num_pb_type_output_port = 0;
t_port** pb_type_output_ports = NULL;
char* formatted_subckt_prefix = format_verilog_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/
t_pb_type* cur_pb_type = NULL;
char* port_prefix = NULL;

86
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c
View File

@ -661,9 +661,9 @@ void build_ending_rr_node_for_one_sb_wire(t_rr_node* wire_rr_node,
*/
static
void verilog_generate_report_timing_one_sb_thru_segments(FILE* fp,
RRGSB src_sb,
const RRGSB& src_sb,
t_rr_node* src_rr_node,
RRGSB des_sb,
const RRGSB& des_sb,
t_rr_node* des_rr_node,
char* rpt_name) {
/* Check the file handler */
@ -759,9 +759,6 @@ void verilog_generate_report_timing_one_sb_ending_segments(FILE* fp,
t_rr_node* src_rr_node,
t_rr_node* des_rr_node,
char* rpt_name) {
t_cb* next_cb = NULL;
DeviceCoordinator next_sb_coordinator;
RRGSB next_sb;
/* Check the file handler */
if (NULL == fp) {
@ -772,20 +769,22 @@ void verilog_generate_report_timing_one_sb_ending_segments(FILE* fp,
}
switch (des_rr_node->type) {
case IPIN:
case IPIN: {
/* Get the coordinate of ending CB */
next_cb = get_chan_rr_node_ending_cb(src_rr_node, des_rr_node);
t_cb* next_cb = get_chan_rr_node_ending_cb(src_rr_node, des_rr_node);
verilog_generate_one_report_timing_sb_to_cb(fp, src_sb, src_rr_node,
next_cb, des_rr_node);
break;
}
case CHANX:
case CHANY:
case CHANY: {
/* Get the coordinate of ending SB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
DeviceCoordinator next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
const RRGSB& next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
verilog_generate_one_report_timing_sb_to_sb(fp, src_sb, src_rr_node,
next_sb, src_rr_node);
break;
}
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid type of ending point rr_node!\n",
__FILE__, __LINE__);
@ -876,7 +875,6 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
t_cb* next_cb = NULL;
char* rpt_name = NULL;
DeviceCoordinator next_sb_coordinator;
RRGSB next_sb;
/* Check the file handler */
if (NULL == fp) {
@ -1006,13 +1004,14 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
* ---------
*/
case CHANX:
case CHANY:
case CHANY: {
/* Get the coordinate of ending CB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
const RRGSB& next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
end_sb_x = next_sb.get_sb_x();
end_sb_y = next_sb.get_sb_y();
break;
}
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid type of rr_node!\n",
__FILE__, __LINE__);
@ -1048,10 +1047,10 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
fprintf(fp, " -unconstrained");
break;
case CHANX:
case CHANY:
case CHANY: {
/* Get the coordinate of ending SB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
const RRGSB& next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
fprintf(fp, " -to ");
@ -1065,6 +1064,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
fprintf(fp, " -unconstrained");
break;
}
/* Verification is done before the loops.*/
default:
break;
@ -1096,10 +1096,10 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
fprintf(fp, " -unconstrained");
break;
case CHANX:
case CHANY:
case CHANY: {
/* Get the coordinate of ending SB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
const RRGSB& next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
fprintf(fp, " -to ");
@ -1113,6 +1113,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
fprintf(fp, " -unconstrained");
break;
}
/* Verification is done before the loops.*/
default:
break;
@ -1144,10 +1145,10 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
fprintf(fp, " -unconstrained");
break;
case CHANX:
case CHANY:
case CHANY: {
/* Get the coordinate of ending SB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
const RRGSB& next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
fprintf(fp, " -to ");
@ -1161,6 +1162,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
fprintf(fp, " -unconstrained");
break;
}
/* Verification is done before the loops.*/
default:
break;
@ -1192,10 +1194,10 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
fprintf(fp, " -unconstrained");
break;
case CHANX:
case CHANY:
case CHANY: {
/* Get the coordinate of ending SB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
const RRGSB& next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
fprintf(fp, " -to ");
@ -1209,6 +1211,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
fprintf(fp, " -unconstrained");
break;
}
/* Verification is done before the loops.*/
default:
break;
@ -1570,7 +1573,6 @@ void dump_verilog_sb_through_routing_pins(FILE* fp,
size_t end_sb_x, end_sb_y;
t_cb* next_cb;
DeviceCoordinator next_sb_coordinator;
RRGSB next_sb;
/* Check the file handler */
if (NULL == fp) {
@ -1682,13 +1684,14 @@ void dump_verilog_sb_through_routing_pins(FILE* fp,
* ---------
*/
case CHANX:
case CHANY:
case CHANY: {
/* Get the coordinate of ending CB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
const RRGSB& next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
end_sb_x = next_sb.get_sb_x();
end_sb_y = next_sb.get_sb_y();
break;
}
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid type of rr_node!\n",
__FILE__, __LINE__);
@ -1707,7 +1710,7 @@ void dump_verilog_sb_through_routing_pins(FILE* fp,
fprintf(fp, " ");
/* output instance name */
DeviceCoordinator inter_sb_coordinator(ix, cur_sb_y);
RRGSB inter_sb = device_rr_gsb.get_gsb(inter_sb_coordinator);
const RRGSB& inter_sb = device_rr_gsb.get_gsb(inter_sb_coordinator);
fprintf(fp, "%s/",
inter_sb.gen_sb_verilog_instance_name());
dump_verilog_one_sb_chan_pin(fp, inter_sb, src_rr_node, IN_PORT);
@ -1726,7 +1729,7 @@ void dump_verilog_sb_through_routing_pins(FILE* fp,
fprintf(fp, " ");
/* output instance name */
DeviceCoordinator inter_sb_coordinator(cur_sb_x, iy);
RRGSB inter_sb = device_rr_gsb.get_gsb(inter_sb_coordinator);
const RRGSB& inter_sb = device_rr_gsb.get_gsb(inter_sb_coordinator);
fprintf(fp, "%s/",
inter_sb.gen_sb_verilog_instance_name());
dump_verilog_one_sb_chan_pin(fp, inter_sb, src_rr_node, IN_PORT);
@ -1745,7 +1748,7 @@ void dump_verilog_sb_through_routing_pins(FILE* fp,
fprintf(fp, " ");
/* output instance name */
DeviceCoordinator inter_sb_coordinator(ix, cur_sb_y);
RRGSB inter_sb = device_rr_gsb.get_gsb(inter_sb_coordinator);
const RRGSB& inter_sb = device_rr_gsb.get_gsb(inter_sb_coordinator);
fprintf(fp, "%s/",
inter_sb.gen_sb_verilog_instance_name());
dump_verilog_one_sb_chan_pin(fp, inter_sb, src_rr_node, IN_PORT);
@ -1764,7 +1767,7 @@ void dump_verilog_sb_through_routing_pins(FILE* fp,
fprintf(fp, " ");
/* output instance name */
DeviceCoordinator inter_sb_coordinator(cur_sb_x, iy);
RRGSB inter_sb = device_rr_gsb.get_gsb(inter_sb_coordinator);
const RRGSB& inter_sb = device_rr_gsb.get_gsb(inter_sb_coordinator);
fprintf(fp, "%s/",
inter_sb.gen_sb_verilog_instance_name());
dump_verilog_one_sb_chan_pin(fp, inter_sb, src_rr_node, IN_PORT);
@ -2020,7 +2023,6 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp,
assert( ( CHANX == wire_rr_node->type )
|| ( CHANY == wire_rr_node->type ));
int track_idx = wire_rr_node->ptc_num;
t_rr_type cb_type = wire_rr_node->type;
/* We only care a specific length of wires */
@ -2040,8 +2042,7 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp,
int inode = wire_rr_node->edges[jedge];
/* Find the SB/CB block that it belongs to */
switch (LL_rr_node[inode].type) {
case IPIN:
{
case IPIN: {
DeviceCoordinator next_cb_coordinator = get_chan_node_ending_cb(wire_rr_node, &(LL_rr_node[inode]));
/* Get the coordinate of ending CB */
const RRGSB& next_cb = device_rr_gsb.get_gsb(next_cb_coordinator);
@ -2067,9 +2068,21 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp,
/* output instance name */
fprintf(fp, "%s/",
next_cb.gen_cb_verilog_instance_name(cb_type));
/* FIXME: we should avoid using global variables !!!! */
/* If we have an mirror SB, we should the module name of the mirror !!! */
DeviceCoordinator coordinator = next_cb.get_cb_coordinator(cb_type);
const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, coordinator);
enum e_side pin_gsb_side = next_cb.get_cb_chan_side(cb_type);
/* We get the index and side for the cur_rr_node in the mother rr_sb context */
int pin_node_id = next_cb.get_chan_node_index(pin_gsb_side, wire_rr_node);
/* Make sure we have valid numbers */
assert ( -1 != pin_node_id );
/* output pin name */
fprintf(fp, "%s",
next_cb.gen_cb_verilog_routing_track_name(cb_type, track_idx));
unique_mirror.gen_cb_verilog_routing_track_name(cb_type, pin_node_id));
/* Print through pins */
if (TRUE == sdc_opts.print_thru_pins) {
fprintf(fp, " -through_pins ");
@ -2079,11 +2092,10 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp,
}
fprintf(fp, " -unconstrained\n");
path_cnt++;
}
break;
}
case CHANX:
case CHANY:
{
case CHANY: {
DeviceCoordinator next_sb_coordinator;
/* Get the coordinate of ending SB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(wire_rr_node, &(LL_rr_node[inode]));
@ -2129,8 +2141,8 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp,
path_cnt++;
/* Set the flag */
sb_dumped = TRUE;
}
break;
}
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid type of ending point rr_node!\n",
__FILE__, __LINE__);
@ -2715,7 +2727,7 @@ void verilog_generate_routing_wire_report_timing(t_trpt_opts trpt_opts,
DeviceCoordinator sb_range = device_rr_gsb.get_gsb_range();
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
RRGSB rr_sb = device_rr_gsb.get_gsb(ix, iy);
const RRGSB& rr_sb = device_rr_gsb.get_gsb(ix, iy);
for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) {
Side side_manager(side);
for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) {

13
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c
View File

@ -678,8 +678,19 @@ void verilog_generate_sdc_constrain_one_cb_path(FILE* fp,
fprintf(fp, " -from ");
fprintf(fp, "%s/",
rr_gsb.gen_cb_verilog_instance_name(cb_type));
/* FIXME: we should avoid using global variables !!!! */
/* If we have an mirror SB, we should the module name of the mirror !!! */
DeviceCoordinator coordinator = rr_gsb.get_cb_coordinator(cb_type);
const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, coordinator);
enum e_side pin_gsb_side = rr_gsb.get_cb_chan_side(cb_type);
/* We get the index and side for the cur_rr_node in the mother rr_sb context */
int pin_node_id = rr_gsb.get_chan_node_index(pin_gsb_side, src_rr_node);
/* Make sure we have valid numbers */
assert ( -1 != pin_node_id );
fprintf(fp, "%s",
rr_gsb.gen_cb_verilog_routing_track_name(cb_type, src_rr_node->ptc_num));
unique_mirror.gen_cb_verilog_routing_track_name(cb_type, pin_node_id));
fprintf(fp, " -to ");