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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb

This commit is contained in:
AurelienUoU 2019-06-14 11:46:02 -06:00
parent c76dbaac33 4d2a3680be
commit 29dadc51b4
3 changed files with 72 additions and 80 deletions
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119
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
View File

@ -350,6 +350,51 @@ void stats_mux_verilog_model_pb_node_rec(t_llist** muxes_head,
return;
}
/* Print a port of pb_types,
* SRAM ports are not printed here!!!
* Important feature: manage the comma between ports
* Make sure there is no redundant comma and there is no comma after the last element if specified
*/
static
void dump_verilog_pb_type_one_bus_port(FILE* fp,
t_pb_type* cur_pb_type,
char* port_prefix,
char* port_type_str,
t_port* pb_type_port,
boolean dump_port_type,
boolean dump_explicit_port_map) {
if (TRUE == dump_port_type) {
fprintf(fp, "%s ", port_type_str);
fprintf(fp, "[0:%d] %s__%s ",
pb_type_port->num_pins - 1,
port_prefix, pb_type_port->name);
} else {
if ((NULL != cur_pb_type->spice_model)
&& (TRUE == dump_explicit_port_map)
&& (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) {
fprintf(fp, ".%s(",
pb_type_port->spice_model_port->lib_name);
}
fprintf(fp, "{");
for (int ipin = 0; ipin < pb_type_port->num_pins; ++ipin) {
if (0 < ipin) {
fprintf(fp, ", ");
}
fprintf(fp, "%s",
gen_verilog_one_pb_type_pin_name(port_prefix, pb_type_port, ipin));
}
fprintf(fp, "}");
if ((NULL != cur_pb_type->spice_model)
&& (TRUE == dump_explicit_port_map)
&& (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) {
fprintf(fp, ")");
}
}
return;
}
/* Print ports of pb_types,
* SRAM ports are not printed here!!!
* Important feature: manage the comma between ports
@ -360,7 +405,8 @@ void dump_verilog_pb_type_bus_ports(FILE* fp,
int use_global_clock,
t_pb_type* cur_pb_type,
boolean dump_port_type,
boolean dump_last_comma) {
boolean dump_last_comma,
boolean dump_explicit_port_map) {
int iport;
int num_pb_type_input_port = 0;
t_port** pb_type_input_ports = NULL;
@ -398,16 +444,9 @@ void dump_verilog_pb_type_bus_ports(FILE* fp,
fprintf(fp, ", ");
}
}
if (TRUE == dump_port_type) {
fprintf(fp, "inout ");
fprintf(fp, "[0:%d] %s__%s ",
pb_type_inout_ports[iport]->num_pins - 1,
formatted_port_prefix, pb_type_inout_ports[iport]->name);
} else {
fprintf(fp, "%s__%s[0:%d] ",
formatted_port_prefix, pb_type_inout_ports[iport]->name,
pb_type_inout_ports[iport]->num_pins - 1);
}
dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "inout",
pb_type_inout_ports[iport], dump_port_type, dump_explicit_port_map);
/* Update the counter */
num_dumped_port++;
}
@ -424,16 +463,8 @@ void dump_verilog_pb_type_bus_ports(FILE* fp,
fprintf(fp, ", ");
}
}
if (TRUE == dump_port_type) {
fprintf(fp, "input ");
fprintf(fp, " [0:%d] %s__%s ",
pb_type_input_ports[iport]->num_pins - 1,
formatted_port_prefix, pb_type_input_ports[iport]->name);
} else {
fprintf(fp, " %s__%s[0:%d] ",
formatted_port_prefix, pb_type_input_ports[iport]->name,
pb_type_input_ports[iport]->num_pins - 1);
}
dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "input",
pb_type_input_ports[iport], dump_port_type, dump_explicit_port_map);
/* Update the counter */
num_dumped_port++;
}
@ -450,44 +481,30 @@ void dump_verilog_pb_type_bus_ports(FILE* fp,
fprintf(fp, ", ");
}
}
if (TRUE == dump_port_type) {
fprintf(fp, "output ");
fprintf(fp, " %s__%s[0:%d]",
formatted_port_prefix, pb_type_output_ports[iport]->name,
pb_type_output_ports[iport]->num_pins - 1);
} else {
fprintf(fp, " %s__%s[0:%d]",
formatted_port_prefix, pb_type_output_ports[iport]->name,
pb_type_output_ports[iport]->num_pins - 1);
}
dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "output",
pb_type_output_ports[iport], dump_port_type, dump_explicit_port_map);
/* Update the counter */
num_dumped_port++;
}
/* Clocks */
/* Find pb_type clock ports */
pb_type_clk_ports = find_pb_type_ports_match_spice_model_port_type(cur_pb_type, SPICE_MODEL_PORT_CLOCK, &num_pb_type_clk_port);
/* Print all the clk ports */
for (iport = 0; iport < num_pb_type_clk_port; iport++) {
if (0 < num_dumped_port) {
if (TRUE == dump_port_type) {
fprintf(fp, ",\n");
} else {
fprintf(fp, ", ");
if (0 == use_global_clock) {
pb_type_clk_ports = find_pb_type_ports_match_spice_model_port_type(cur_pb_type, SPICE_MODEL_PORT_CLOCK, &num_pb_type_clk_port);
/* Print all the clk ports */
for (iport = 0; iport < num_pb_type_clk_port; iport++) {
if (0 < num_dumped_port) {
if (TRUE == dump_port_type) {
fprintf(fp, ",\n");
} else {
fprintf(fp, ", ");
}
}
dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "input",
pb_type_clk_ports[iport], dump_port_type, dump_explicit_port_map);
/* Update the counter */
num_dumped_port++;
}
if (TRUE == dump_port_type) {
fprintf(fp, "input");
fprintf(fp, " %s__%s[0:%d]",
formatted_port_prefix, pb_type_clk_ports[iport]->name,
pb_type_output_ports[iport]->num_pins - 1);
} else {
fprintf(fp, " %s__%s[0:%d]",
formatted_port_prefix, pb_type_clk_ports[iport]->name,
pb_type_output_ports[iport]->num_pins - 1);
}
/* Update the counter */
num_dumped_port++;
}
/* Dump the last comma, when the option is enabled and there is something dumped */

3
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h
View File

@ -23,7 +23,8 @@ void dump_verilog_pb_type_bus_ports(FILE* fp,
int use_global_clock,
t_pb_type* cur_pb_type,
boolean dump_port_type,
boolean dump_last_comma);
boolean dump_last_comma,
boolean dump_explicit_port_map);
void dump_verilog_pb_type_ports(FILE* fp,
char* port_prefix,

30
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c
View File

@ -235,7 +235,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
/* assert */
num_sram = count_num_sram_bits_one_spice_model(verilog_model, -1);
/* print ports --> input ports */
dump_verilog_pb_type_ports(fp, port_prefix, 0, prim_pb_type, FALSE, FALSE, verilog_model->dump_explicit_port_map);
dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, prim_pb_type, FALSE, FALSE, verilog_model->dump_explicit_port_map);
/* IOPADs requires a specical port to output */
if (SPICE_MODEL_IOPAD == verilog_model->type) {
@ -573,32 +573,6 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, ");\n");
/* Definition ends*/
/* Specify inputs are wires */
pb_type_input_ports = find_pb_type_ports_match_spice_model_port_type(cur_pb_type, SPICE_MODEL_PORT_INPUT, &num_pb_type_input_port);
assert(1 == num_pb_type_input_port);
fprintf(fp, "wire [0:%d] %s__%s;\n",
input_ports[0]->size - 1, port_prefix, pb_type_input_ports[0]->name);
for (i = 0; i < input_ports[0]->size; i++) {
fprintf(fp, "assign %s__%s[%d] = %s__%s_%d_;\n",
port_prefix, pb_type_input_ports[0]->name, i,
port_prefix, pb_type_input_ports[0]->name, i);
}
/* Specify outputs are wires */
pb_type_output_ports = find_pb_type_ports_match_spice_model_port_type(cur_pb_type, SPICE_MODEL_PORT_OUTPUT, &num_pb_type_output_port);
for (i = 0; i < num_pb_type_output_port; i++) {
fprintf(fp, "wire [0:%d] %s__%s;\n",
output_ports[i]->size - 1, port_prefix, pb_type_output_ports[i]->name);
}
/* Make sure we have the same number outputs */
assert (num_pb_type_output_port == num_output_port);
for (i = 0; i < num_output_port; i++) {
for (ipin = 0; ipin < output_ports[i]->size; ipin++) {
fprintf(fp, "assign %s__%s_%d_ = %s__%s[%d];\n",
port_prefix, pb_type_output_ports[i]->name, ipin,
port_prefix, pb_type_output_ports[i]->name, ipin);
}
}
/* Specify SRAM output are wires */
cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info);
dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_sram - 1);
@ -640,7 +614,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
/* Connect inputs*/
/* Connect outputs*/
fprintf(fp, "//----- Input and output ports -----\n");
dump_verilog_pb_type_bus_ports(fp, port_prefix, 0, cur_pb_type, FALSE, TRUE);
dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, cur_pb_type, FALSE, TRUE, verilog_model->dump_explicit_port_map);
fprintf(fp, "\n//----- SRAM ports -----\n");
/* check */