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use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB

This commit is contained in:
tangxifan 2019-06-10 12:50:10 -06:00
parent e31407f693
commit 8a8f4153ce
13 changed files with 541 additions and 191 deletions
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1
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c
View File

@ -1395,6 +1395,7 @@ void fpga_x2p_setup(t_vpr_setup vpr_setup,
/* Try to use mirror SBs/CBs if enabled by user */
if (TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy) {
/* Idenify mirror and rotatable Switch blocks and Connection blocks */
identify_mirror_switch_blocks();
identify_mirror_connection_blocks();

32
vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp
View File

@ -2166,13 +2166,13 @@ DeviceCoordinator DeviceRRGSB::get_gsb_range() const {
}
/* Get a rr switch block in the array with a coordinator */
RRGSB DeviceRRGSB::get_gsb(DeviceCoordinator& coordinator) const {
const RRGSB DeviceRRGSB::get_gsb(DeviceCoordinator& coordinator) const {
assert(validate_coordinator(coordinator));
return rr_gsb_[coordinator.get_x()][coordinator.get_y()];
}
/* Get a rr switch block in the array with a coordinator */
RRGSB DeviceRRGSB::get_gsb(size_t x, size_t y) const {
const RRGSB DeviceRRGSB::get_gsb(size_t x, size_t y) const {
DeviceCoordinator coordinator(x, y);
return get_gsb(coordinator);
}
@ -2221,7 +2221,7 @@ size_t DeviceRRGSB::get_sb_unique_submodule_id(DeviceCoordinator& coordinator, e
}
/* Get a rr switch block which is a unique module of a side of SB */
RRGSB DeviceRRGSB::get_sb_unique_submodule(size_t index, enum e_side side, size_t seg_id) const {
const RRGSB DeviceRRGSB::get_sb_unique_submodule(size_t index, enum e_side side, size_t seg_id) const {
assert (validate_sb_unique_submodule_index(index, side, seg_id));
Side side_manager(side);
@ -2234,7 +2234,7 @@ RRGSB DeviceRRGSB::get_sb_unique_submodule(size_t index, enum e_side side, size_
}
/* Get a rr switch block which is a unique module of a side of SB */
RRGSB DeviceRRGSB::get_sb_unique_submodule(DeviceCoordinator& coordinator, enum e_side side, size_t seg_id) const {
const RRGSB DeviceRRGSB::get_sb_unique_submodule(DeviceCoordinator& coordinator, enum e_side side, size_t seg_id) const {
assert (validate_coordinator(coordinator));
Side side_manager(side);
@ -2247,21 +2247,21 @@ RRGSB DeviceRRGSB::get_sb_unique_submodule(DeviceCoordinator& coordinator, enum
/* Get a rr switch block which a unique mirror */
RRGSB DeviceRRGSB::get_sb_unique_module(size_t index) const {
const RRGSB DeviceRRGSB::get_sb_unique_module(size_t index) const {
assert (validate_sb_unique_module_index(index));
return rr_gsb_[sb_unique_module_[index].get_x()][sb_unique_module_[index].get_y()];
}
/* Get a rr switch block which a unique mirror */
RRGSB DeviceRRGSB::get_cb_unique_module(t_rr_type cb_type, size_t index) const {
const RRGSB DeviceRRGSB::get_cb_unique_module(t_rr_type cb_type, size_t index) const {
assert (validate_cb_unique_module_index(cb_type, index));
assert (validate_cb_type(cb_type));
switch(cb_type) {
case CHANX:
return rr_gsb_[cbx_unique_module_[index].get_x()][cbx_unique_module_[index].get_y()];
case CHANX:
return rr_gsb_[cbx_unique_module_[index].get_x()][cbx_unique_module_[index].get_y()];
case CHANY:
return rr_gsb_[cby_unique_module_[index].get_x()][cby_unique_module_[index].get_y()];
return rr_gsb_[cby_unique_module_[index].get_x()][cby_unique_module_[index].get_y()];
default:
vpr_printf(TIO_MESSAGE_ERROR,
"(File:%s, [LINE%d])Invalid type of connection block!\n",
@ -2271,7 +2271,7 @@ RRGSB DeviceRRGSB::get_cb_unique_module(t_rr_type cb_type, size_t index) const {
}
/* Give a coordinator of a rr switch block, and return its unique mirror */
RRGSB DeviceRRGSB::get_cb_unique_module(t_rr_type cb_type, DeviceCoordinator& coordinator) const {
const RRGSB DeviceRRGSB::get_cb_unique_module(t_rr_type cb_type, DeviceCoordinator& coordinator) const {
assert (validate_cb_type(cb_type));
assert(validate_coordinator(coordinator));
size_t cb_unique_module_id;
@ -2294,7 +2294,7 @@ RRGSB DeviceRRGSB::get_cb_unique_module(t_rr_type cb_type, DeviceCoordinator& co
}
/* Give a coordinator of a rr switch block, and return its unique mirror */
RRGSB DeviceRRGSB::get_sb_unique_module(DeviceCoordinator& coordinator) const {
const RRGSB DeviceRRGSB::get_sb_unique_module(DeviceCoordinator& coordinator) const {
assert(validate_coordinator(coordinator));
size_t sb_unique_module_id = sb_unique_module_id_[coordinator.get_x()][coordinator.get_y()];
return get_sb_unique_module(sb_unique_module_id);
@ -2413,7 +2413,7 @@ void DeviceRRGSB::reserve(DeviceCoordinator& coordinator) {
/* Pre-allocate the rr_sb_unique_module_id matrix that the device requires */
void DeviceRRGSB::reserve_sb_unique_submodule_id(DeviceCoordinator& coordinator) {
RRGSB rr_sb = get_gsb(coordinator);
const RRGSB& rr_sb = get_gsb(coordinator);
sb_unique_submodule_id_[coordinator.get_x()][coordinator.get_y()].resize(rr_sb.get_num_sides());
for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) {
@ -2450,7 +2450,7 @@ void DeviceRRGSB::resize_upon_need(DeviceCoordinator& coordinator) {
/* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
void DeviceRRGSB::add_rr_gsb(DeviceCoordinator& coordinator,
RRGSB& rr_gsb) {
const RRGSB& rr_gsb) {
/* Resize upon needs*/
resize_upon_need(coordinator);
@ -2549,7 +2549,7 @@ void DeviceRRGSB::build_sb_unique_submodule() {
for (size_t ix = 0; ix < rr_gsb_.size(); ++ix) {
for (size_t iy = 0; iy < rr_gsb_[ix].size(); ++iy) {
DeviceCoordinator coordinator(ix, iy);
RRGSB rr_sb = rr_gsb_[ix][iy];
const RRGSB& rr_sb = rr_gsb_[ix][iy];
/* reserve the rr_sb_unique_module_id */
reserve_sb_unique_submodule_id(coordinator);
@ -2565,7 +2565,7 @@ void DeviceRRGSB::build_sb_unique_submodule() {
}
void DeviceRRGSB::add_sb_unique_side_segment_submodule(DeviceCoordinator& coordinator,
RRGSB& rr_sb,
const RRGSB& rr_sb,
enum e_side side,
size_t seg_id) {
bool is_unique_side_module = true;
@ -2613,7 +2613,7 @@ void DeviceRRGSB::build_unique_module() {
* Otherwise, we add the module to the unique_module list
*/
void DeviceRRGSB::add_sb_unique_side_submodule(DeviceCoordinator& coordinator,
RRGSB& rr_sb,
const RRGSB& rr_sb,
enum e_side side) {
Side side_manager(side);

22
vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h
View File

@ -284,18 +284,18 @@ class DeviceRRGSB {
public: /* Contructors */
public: /* Accessors */
DeviceCoordinator get_gsb_range() const; /* get the max coordinator of the switch block array */
RRGSB get_gsb(DeviceCoordinator& coordinator) const; /* Get a rr switch block in the array with a coordinator */
RRGSB get_gsb(size_t x, size_t y) const; /* Get a rr switch block in the array with a coordinator */
const RRGSB get_gsb(DeviceCoordinator& coordinator) const; /* Get a rr switch block in the array with a coordinator */
const RRGSB get_gsb(size_t x, size_t y) const; /* Get a rr switch block in the array with a coordinator */
size_t get_num_sb_unique_submodule(enum e_side side, size_t seg_index) const; /* get the number of unique mirrors of switch blocks */
size_t get_num_sb_unique_module() const; /* get the number of unique mirrors of switch blocks */
size_t get_num_cb_unique_module(t_rr_type cb_type) const; /* get the number of unique mirrors of CBs */
size_t get_sb_unique_submodule_id(DeviceCoordinator& coordinator, enum e_side side, size_t seg_id) const;
RRGSB get_sb_unique_submodule(size_t index, enum e_side side, size_t seg_id) const; /* Get a rr switch block which a unique mirror */
RRGSB get_sb_unique_submodule(DeviceCoordinator& coordinator, enum e_side side, size_t seg_id) const; /* Get a rr switch block which a unique mirror */
RRGSB get_sb_unique_module(size_t index) const; /* Get a rr switch block which a unique mirror */
RRGSB get_sb_unique_module(DeviceCoordinator& coordinator) const; /* Get a rr switch block which a unique mirror */
RRGSB get_cb_unique_module(t_rr_type cb_type, size_t index) const; /* Get a rr switch block which a unique mirror */
RRGSB get_cb_unique_module(t_rr_type cb_type, DeviceCoordinator& coordinator) const;
const RRGSB get_sb_unique_submodule(size_t index, enum e_side side, size_t seg_id) const; /* Get a rr switch block which a unique mirror */
const RRGSB get_sb_unique_submodule(DeviceCoordinator& coordinator, enum e_side side, size_t seg_id) const; /* Get a rr switch block which a unique mirror */
const RRGSB get_sb_unique_module(size_t index) const; /* Get a rr switch block which a unique mirror */
const RRGSB get_sb_unique_module(DeviceCoordinator& coordinator) const; /* Get a rr switch block which a unique mirror */
const RRGSB get_cb_unique_module(t_rr_type cb_type, size_t index) const; /* Get a rr switch block which a unique mirror */
const RRGSB get_cb_unique_module(t_rr_type cb_type, DeviceCoordinator& coordinator) const;
size_t get_max_num_sides() const; /* Get the maximum number of sides across the switch blocks */
size_t get_num_segments() const; /* Get the size of segment_ids */
size_t get_segment_id(size_t index) const; /* Get a segment id */
@ -310,7 +310,7 @@ class DeviceRRGSB {
void reserve(DeviceCoordinator& coordinator); /* Pre-allocate the rr_switch_block array that the device requires */
void reserve_sb_unique_submodule_id(DeviceCoordinator& coordinator); /* Pre-allocate the rr_sb_unique_module_id matrix that the device requires */
void resize_upon_need(DeviceCoordinator& coordinator); /* Resize the rr_switch_block array if needed */
void add_rr_gsb(DeviceCoordinator& coordinator, RRGSB& rr_gsb); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
void add_rr_gsb(DeviceCoordinator& coordinator, const RRGSB& rr_gsb); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
void build_unique_module(); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
void clear(); /* clean the content */
private: /* Internal cleaners */
@ -332,8 +332,8 @@ class DeviceRRGSB {
bool validate_cb_type(t_rr_type cb_type) const;
private: /* Internal builders */
void build_segment_ids(); /* build a map of segment_ids */
void add_sb_unique_side_submodule(DeviceCoordinator& coordinator, RRGSB& rr_sb, enum e_side side);
void add_sb_unique_side_segment_submodule(DeviceCoordinator& coordinator, RRGSB& rr_sb, enum e_side side, size_t seg_id);
void add_sb_unique_side_submodule(DeviceCoordinator& coordinator, const RRGSB& rr_sb, enum e_side side);
void add_sb_unique_side_segment_submodule(DeviceCoordinator& coordinator, const RRGSB& rr_sb, enum e_side side, size_t seg_id);
void add_cb_unique_module(t_rr_type cb_type, const DeviceCoordinator& coordinator);
void set_cb_unique_module_id(t_rr_type, const DeviceCoordinator& coordinator, size_t id);
void build_sb_unique_submodule(); /* Add a switch block to the array, which will automatically identify and update the lists of unique side module */

18
vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_routing.c
View File

@ -38,7 +38,7 @@
/* Generate bitstream for a multiplexer of a switch block */
static
void fpga_spice_generate_bitstream_switch_box_mux(FILE* fp,
RRGSB& rr_sb,
const RRGSB& rr_sb,
t_sram_orgz_info* cur_sram_orgz_info,
t_rr_node* cur_rr_node,
int mux_size,
@ -213,7 +213,7 @@ void fpga_spice_generate_bitstream_switch_box_mux(FILE* fp,
static
void fpga_spice_generate_bitstream_switch_box_interc(FILE* fp,
RRGSB& rr_sb,
const RRGSB& rr_sb,
t_sram_orgz_info* cur_sram_orgz_info,
enum e_side chan_side,
t_rr_node* cur_rr_node) {
@ -344,7 +344,7 @@ void fpga_spice_generate_bitstream_switch_box_interc(FILE* fp,
*/
static
void fpga_spice_generate_bitstream_routing_switch_box_subckt(FILE* fp,
RRGSB& rr_sb,
const RRGSB& rr_sb,
t_sram_orgz_info* cur_sram_orgz_info) {
/* Check */
/* Check the file handler*/
@ -450,7 +450,7 @@ void fpga_spice_generate_bitstream_routing_switch_box_subckt(FILE* fp,
/* SRC rr_node is the IPIN of a grid.*/
static
void fpga_spice_generate_bitstream_connection_box_mux(FILE* fp,
RRGSB& rr_gsb, t_rr_type cb_type,
const RRGSB& rr_gsb, t_rr_type cb_type,
t_sram_orgz_info* cur_sram_orgz_info,
t_rr_node* src_rr_node) {
int mux_size = 0;
@ -652,7 +652,7 @@ void fpga_spice_generate_bitstream_connection_box_interc(FILE* fp,
static
void fpga_spice_generate_bitstream_connection_box_interc(FILE* fp,
RRGSB& rr_gsb, t_rr_type cb_type,
const RRGSB& rr_gsb, t_rr_type cb_type,
t_sram_orgz_info* cur_sram_orgz_info,
t_rr_node* src_rr_node) {
@ -700,7 +700,7 @@ void fpga_spice_generate_bitstream_connection_box_interc(FILE* fp,
*/
static
void fpga_spice_generate_bitstream_routing_connection_box_subckt(FILE* fp,
RRGSB& rr_gsb, t_rr_type cb_type,
const RRGSB& rr_gsb, t_rr_type cb_type,
t_sram_orgz_info* cur_sram_orgz_info) {
/* Check the file handler*/
@ -840,7 +840,7 @@ void fpga_spice_generate_bitstream_routing_resources(char* routing_bitstream_log
DeviceCoordinator sb_range = device_rr_gsb.get_gsb_range();
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
RRGSB rr_sb = device_rr_gsb.get_gsb(ix, iy);
const RRGSB& rr_sb = device_rr_gsb.get_gsb(ix, iy);
fpga_spice_generate_bitstream_routing_switch_box_subckt(fp,
rr_sb, cur_sram_orgz_info);
}
@ -863,7 +863,7 @@ void fpga_spice_generate_bitstream_routing_resources(char* routing_bitstream_log
/* X - channels [1...nx][0..ny]*/
for (int iy = 0; iy < (ny + 1); ++iy) {
for (int ix = 1; ix < (nx + 1); ++ix) {
RRGSB rr_gsb = device_rr_gsb.get_gsb(ix, iy);
const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
if ((TRUE == is_cb_exist(CHANX, ix, iy))
&&(true == rr_gsb.is_cb_exist(CHANX))) {
fpga_spice_generate_bitstream_routing_connection_box_subckt(fp,
@ -876,7 +876,7 @@ void fpga_spice_generate_bitstream_routing_resources(char* routing_bitstream_log
vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for Connection blocks - Y direction ...\n");
for (int ix = 0; ix < (nx + 1); ++ix) {
for (int iy = 1; iy < (ny + 1); ++iy) {
RRGSB rr_gsb = device_rr_gsb.get_gsb(ix, iy);
const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
if ((TRUE == is_cb_exist(CHANY, ix, iy))
&&(true == rr_gsb.is_cb_exist(CHANY))) {
fpga_spice_generate_bitstream_routing_connection_box_subckt(fp,

4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c
View File

@ -286,7 +286,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup,
verilog_generate_sdc_pnr(sram_verilog_orgz_info, sdc_dir_path,
Arch, &vpr_setup.RoutingArch,
num_rr_nodes, rr_node, rr_node_indices, rr_indexed_data,
nx, ny,
nx, ny, device_rr_gsb,
vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy);
}
@ -384,7 +384,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup,
verilog_generate_sdc_analysis(sram_verilog_orgz_info, sdc_dir_path,
Arch,
num_rr_nodes, rr_node, rr_node_indices,
nx, ny, grid, block,
nx, ny, grid, block, device_rr_gsb,
vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy);
}
/* Output routing report_timing script :

21
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
View File

@ -749,7 +749,7 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info,
static
void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
RRGSB& rr_sb) {
const RRGSB& rr_sb) {
/* Check the file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n",
@ -766,7 +766,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz
/* If we have an mirror SB, we should the module name of the mirror !!! */
DeviceCoordinator coordinator = rr_sb.get_sb_coordinator();
RRGSB unique_mirror = device_rr_gsb.get_sb_unique_module(coordinator);
const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(coordinator);
fprintf(fp, "%s ", unique_mirror.gen_sb_verilog_module_name());
fprintf(fp, "%s ", rr_sb.gen_sb_verilog_instance_name());
fprintf(fp, "(");
@ -861,7 +861,7 @@ void dump_compact_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_i
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
RRGSB rr_sb = device_rr_gsb.get_gsb(ix, iy);
const RRGSB& rr_sb = device_rr_gsb.get_gsb(ix, iy);
dump_compact_verilog_defined_one_switch_box(cur_sram_orgz_info, fp, rr_sb);
}
}
@ -877,7 +877,7 @@ void dump_compact_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_i
static
void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
RRGSB& rr_gsb, t_rr_type cb_type) {
const RRGSB& rr_gsb, t_rr_type cb_type) {
/* Check the file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n",
@ -892,7 +892,7 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_
/* If we have an mirror SB, we should the module name of the mirror !!! */
DeviceCoordinator coordinator = rr_gsb.get_sb_coordinator();
RRGSB unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, coordinator);
const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, coordinator);
fprintf(fp, "%s ", unique_mirror.gen_cb_verilog_module_name(cb_type));
fprintf(fp, "%s ", rr_gsb.gen_cb_verilog_instance_name(cb_type));
fprintf(fp, "(");
@ -920,12 +920,13 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_
fprintf(fp, "//----- %s side outputs: CLB input pins -----\n",
side_manager.c_str());
for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) {
t_rr_node* cur_ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode);
/* Print each INPUT Pins of a grid */
dump_verilog_grid_side_pin_with_given_index(fp, OPIN,
rr_gsb.get_ipin_node(cb_ipin_side, inode)->ptc_num,
cur_ipin_node->ptc_num,
rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode),
rr_gsb.get_ipin_node(cb_ipin_side, inode)->xlow,
rr_gsb.get_ipin_node(cb_ipin_side, inode)->ylow,
cur_ipin_node->xlow,
cur_ipin_node->ylow,
FALSE); /* Do not specify direction of port */
fprintf(fp, ", \n");
}
@ -985,7 +986,7 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or
/* X - channels [1...nx][0..ny]*/
for (iy = 0; iy < (ny + 1); iy++) {
for (ix = 1; ix < (nx + 1); ix++) {
RRGSB rr_gsb = device_rr_gsb.get_gsb(ix, iy);
const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
if ((TRUE == is_cb_exist(CHANX, ix, iy))
&&(true == rr_gsb.is_cb_exist(CHANX))) {
dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANX);
@ -995,7 +996,7 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or
/* Y - channels [1...ny][0..nx]*/
for (ix = 0; ix < (nx + 1); ix++) {
for (iy = 1; iy < (ny + 1); iy++) {
RRGSB rr_gsb = device_rr_gsb.get_gsb(ix, iy);
const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
if ((TRUE == is_cb_exist(CHANY, ix, iy))
&&(true == rr_gsb.is_cb_exist(CHANY))) {
dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANY);

18
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c
View File

@ -245,7 +245,7 @@ void free_wire_L_llist(t_llist* rr_path_cnt) {
*/
static
void verilog_generate_one_report_timing_within_sb(FILE* fp,
RRGSB& rr_sb,
const RRGSB& rr_sb,
t_rr_node* src_rr_node,
t_rr_node* des_rr_node) {
/* Check the file handler */
@ -371,7 +371,7 @@ void verilog_generate_one_report_timing_sb_to_cb(FILE* fp,
*/
static
void verilog_generate_one_report_timing_sb_to_cb(FILE* fp,
RRGSB& src_sb,
const RRGSB& src_sb,
t_rr_node* src_rr_node,
t_cb* des_cb_info,
t_rr_node* des_rr_node) {
@ -413,9 +413,9 @@ void verilog_generate_one_report_timing_sb_to_cb(FILE* fp,
*/
static
void verilog_generate_one_report_timing_sb_to_sb(FILE* fp,
RRGSB& src_sb,
const RRGSB& src_sb,
t_rr_node* src_rr_node,
RRGSB& des_sb,
const RRGSB& des_sb,
t_rr_node* des_rr_node) {
/* Check the file handler */
if (NULL == fp) {
@ -692,7 +692,7 @@ void verilog_generate_report_timing_one_sb_thru_segments(FILE* fp,
*/
static
void verilog_generate_report_timing_one_sb_ending_segments(FILE* fp,
RRGSB& src_sb,
const RRGSB& src_sb,
t_rr_node* src_rr_node,
t_rr_node* des_rr_node,
char* rpt_name) {
@ -801,7 +801,7 @@ void verilog_generate_report_timing_one_sb_ending_segments(FILE* fp,
static
void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
t_syn_verilog_opts fpga_verilog_opts,
RRGSB& src_sb,
const RRGSB& src_sb,
t_rr_node* drive_rr_node,
t_rr_node* src_rr_node,
t_rr_node* des_rr_node,
@ -1310,7 +1310,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
*/
static
void dump_verilog_sb_through_routing_pins(FILE* fp,
RRGSB& src_rr_sb,
const RRGSB& src_rr_sb,
t_rr_node* src_rr_node,
t_rr_node* des_rr_node) {
size_t cur_sb_x, cur_sb_y;
@ -1751,7 +1751,7 @@ static
void verilog_generate_one_routing_wire_report_timing(FILE* fp,
t_trpt_opts sdc_opts,
int L_wire,
RRGSB& rr_sb,
const RRGSB& rr_sb,
t_rr_node* wire_rr_node,
t_rr_node* LL_rr_node) {
int path_cnt = 0;
@ -2195,7 +2195,7 @@ void verilog_generate_sb_report_timing(t_trpt_opts sdc_opts,
static
void verilog_generate_one_routing_segmental_report_timing(FILE* fp,
t_syn_verilog_opts fpga_verilog_opts,
RRGSB& rr_sb,
const RRGSB& rr_sb,
t_rr_node* wire_rr_node,
t_rr_node* LL_rr_node,
int* path_cnt) {

218
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
View File

@ -662,7 +662,7 @@ void dump_verilog_switch_box_chan_port(FILE* fp,
static
void dump_verilog_unique_switch_box_chan_port(FILE* fp,
RRGSB& rr_sb,
const RRGSB& rr_sb,
enum e_side chan_side,
t_rr_node* cur_rr_node,
enum PORTS cur_rr_node_direction) {
@ -704,7 +704,7 @@ void dump_verilog_unique_switch_box_chan_port(FILE* fp,
*/
static
void dump_verilog_unique_switch_box_short_interc(FILE* fp,
RRGSB& rr_sb,
const RRGSB& rr_sb,
enum e_side chan_side,
t_rr_node* cur_rr_node,
int actual_fan_in,
@ -1135,7 +1135,7 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
static
void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
RRGSB& rr_sb,
const RRGSB& rr_sb,
enum e_side chan_side,
t_rr_node* cur_rr_node,
int mux_size,
@ -1411,7 +1411,7 @@ int count_verilog_switch_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz_in
/* Count the number of configuration bits of a rr_node*/
static
size_t count_verilog_switch_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
RRGSB& rr_sb, enum e_side chan_side,
const RRGSB& rr_sb, enum e_side chan_side,
t_rr_node* cur_rr_node) {
size_t num_conf_bits = 0;
int switch_idx = 0;
@ -1486,7 +1486,7 @@ int count_verilog_switch_box_interc_reserved_conf_bits(t_sram_orgz_info* cur_sra
/* Count the number of reserved configuration bits of a rr_node*/
static
size_t count_verilog_switch_box_interc_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
RRGSB& rr_sb, enum e_side chan_side,
const RRGSB& rr_sb, enum e_side chan_side,
t_rr_node* cur_rr_node) {
size_t num_reserved_conf_bits = 0;
int switch_idx = 0;
@ -1579,7 +1579,7 @@ void dump_verilog_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
static
void dump_verilog_unique_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
RRGSB& rr_sb,
const RRGSB& rr_sb,
enum e_side chan_side,
t_rr_node* cur_rr_node) {
int num_drive_rr_nodes = 0;
@ -1661,7 +1661,7 @@ int count_verilog_switch_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_
/* Count the number of configuration bits of a Switch Box */
static
size_t count_verilog_switch_box_side_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
RRGSB& rr_sb, enum e_side side, size_t seg_id) {
const RRGSB& rr_sb, enum e_side side, size_t seg_id) {
size_t num_reserved_conf_bits = 0;
size_t temp_num_reserved_conf_bits = 0;
Side side_manager(side);
@ -1696,7 +1696,7 @@ size_t count_verilog_switch_box_side_reserved_conf_bits(t_sram_orgz_info* cur_sr
/* Count the number of configuration bits of a Switch Box */
static
size_t count_verilog_switch_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
RRGSB& rr_sb) {
const RRGSB& rr_sb) {
size_t num_reserved_conf_bits = 0;
size_t temp_num_reserved_conf_bits = 0;
@ -1745,7 +1745,7 @@ int count_verilog_switch_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
/* Count the number of configuration bits of a Switch Box */
static
size_t count_verilog_switch_box_side_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
RRGSB& rr_sb,
const RRGSB& rr_sb,
enum e_side side, size_t seg_id) {
size_t num_conf_bits = 0;
Side side_manager(side);
@ -1776,7 +1776,7 @@ size_t count_verilog_switch_box_side_conf_bits(t_sram_orgz_info* cur_sram_orgz_i
/* Count the number of configuration bits of a Switch Box */
static
size_t count_verilog_switch_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
RRGSB& rr_sb) {
const RRGSB& rr_sb) {
size_t num_conf_bits = 0;
for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) {
@ -1793,7 +1793,7 @@ size_t count_verilog_switch_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
static
void update_routing_switch_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
RRGSB& rr_sb) {
const RRGSB& rr_sb) {
int cur_num_bl, cur_num_wl;
get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_num_bl, &cur_num_wl);
@ -1821,7 +1821,7 @@ void update_routing_switch_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
static
void update_routing_connection_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
RRGSB& rr_gsb, t_rr_type cb_type) {
const RRGSB& rr_gsb, t_rr_type cb_type) {
int cur_num_bl, cur_num_wl;
get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_num_bl, &cur_num_wl);
@ -1854,7 +1854,7 @@ void update_routing_connection_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_inf
*/
static
void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp,
RRGSB& rr_sb,
const RRGSB& rr_sb,
enum e_side sb_side,
size_t seg_id,
boolean dump_port_type) {
@ -1976,7 +1976,7 @@ static
void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir, char* subckt_dir,
size_t module_id, size_t seg_id,
RRGSB& rr_sb, enum e_side side) {
const RRGSB& rr_sb, enum e_side side) {
FILE* fp = NULL;
char* fname = NULL;
Side side_manager(side);
@ -2122,7 +2122,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr
static
void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir, char* subckt_dir,
RRGSB& rr_sb) {
const RRGSB& rr_sb) {
FILE* fp = NULL;
char* fname = NULL;
@ -2132,62 +2132,63 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
int num_reserved_conf_bits = count_verilog_switch_box_reserved_conf_bits(cur_sram_orgz_info, rr_sb);
/* Estimate the sram_verilog_model->cnt */
int cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info);
rr_sb.set_sb_num_reserved_conf_bits(num_reserved_conf_bits);
rr_sb.set_sb_conf_bits_lsb(cur_num_sram);
rr_sb.set_sb_conf_bits_msb(cur_num_sram + num_conf_bits - 1);
RRGSB rr_gsb = rr_sb; /* IMPORTANT: this copy will be removed when the config ports are initialized when created!!! */
rr_gsb.set_sb_num_reserved_conf_bits(num_reserved_conf_bits);
rr_gsb.set_sb_conf_bits_lsb(cur_num_sram);
rr_gsb.set_sb_conf_bits_msb(cur_num_sram + num_conf_bits - 1);
/* Create file handler */
fp = verilog_create_one_subckt_file(subckt_dir, "Unique Switch Block ",
sb_verilog_file_name_prefix, rr_sb.get_sb_x(), rr_sb.get_sb_y(), &fname);
sb_verilog_file_name_prefix, rr_gsb.get_sb_x(), rr_gsb.get_sb_y(), &fname);
/* Print preprocessing flags */
verilog_include_defines_preproc_file(fp, verilog_dir);
/* Comment lines */
fprintf(fp, "//----- Verilog Module of Unique Switch Box[%lu][%lu] -----\n", rr_sb.get_sb_x(), rr_sb.get_sb_y());
fprintf(fp, "//----- Verilog Module of Unique Switch Box[%lu][%lu] -----\n", rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
/* Print the definition of subckt*/
fprintf(fp, "module %s ( \n", rr_sb.gen_sb_verilog_module_name());
fprintf(fp, "module %s ( \n", rr_gsb.gen_sb_verilog_module_name());
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
fprintf(fp, ",\n");
}
for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) {
for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
Side side_manager(side);
/* Print ports */
fprintf(fp, "//----- Channel Inputs/outputs of %s side -----\n", side_manager.c_str());
DeviceCoordinator port_coordinator = rr_sb.get_side_block_coordinator(side_manager.get_side());
DeviceCoordinator port_coordinator = rr_gsb.get_side_block_coordinator(side_manager.get_side());
for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) {
switch (rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)) {
for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) {
switch (rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) {
case OUT_PORT:
fprintf(fp, " output %s,\n",
gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack),
gen_verilog_routing_channel_one_pin_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack),
port_coordinator.get_x(), port_coordinator.get_y(), itrack,
rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)));
rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)));
break;
case IN_PORT:
fprintf(fp, " input %s,\n",
gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack),
gen_verilog_routing_channel_one_pin_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack),
port_coordinator.get_x(), port_coordinator.get_y(), itrack,
rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)));
rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)));
break;
default:
vpr_printf(TIO_MESSAGE_ERROR,
"(File: %s [LINE%d]) Invalid direction of chan[%d][%d]_track[%d]!\n",
__FILE__, __LINE__, rr_sb.get_sb_x(), rr_sb.get_sb_y(), itrack);
__FILE__, __LINE__, rr_gsb.get_sb_x(), rr_gsb.get_sb_y(), itrack);
exit(1);
}
}
/* Dump OPINs of adjacent CLBs */
fprintf(fp, "//----- Grid Inputs/outputs of %s side -----\n", side_manager.c_str());
for (size_t inode = 0; inode < rr_sb.get_num_opin_nodes(side_manager.get_side()); ++inode) {
for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) {
fprintf(fp, " ");
dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an input of a SB */
rr_sb.get_opin_node(side_manager.get_side(), inode)->ptc_num,
rr_sb.get_opin_node_grid_side(side_manager.get_side(), inode),
rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow,
rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow,
rr_gsb.get_opin_node(side_manager.get_side(), inode)->ptc_num,
rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode),
rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow,
rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow,
TRUE); /* Dump the direction of the port ! */
}
}
@ -2196,29 +2197,29 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
/* output of each configuration bit */
/* Reserved sram ports */
fprintf(fp, "//----- Reserved SRAM Ports -----\n");
if (0 < rr_sb.get_sb_num_reserved_conf_bits()) {
if (0 < rr_gsb.get_sb_num_reserved_conf_bits()) {
dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info,
rr_sb.get_sb_reserved_conf_bits_lsb(),
rr_sb.get_sb_reserved_conf_bits_msb(),
rr_gsb.get_sb_reserved_conf_bits_lsb(),
rr_gsb.get_sb_reserved_conf_bits_msb(),
VERILOG_PORT_INPUT);
fprintf(fp, ",\n");
}
/* Normal sram ports */
fprintf(fp, "//----- Regular SRAM Ports -----\n");
dump_verilog_sram_ports(fp, cur_sram_orgz_info,
rr_sb.get_sb_conf_bits_lsb(),
rr_sb.get_sb_conf_bits_msb(),
rr_gsb.get_sb_conf_bits_lsb(),
rr_gsb.get_sb_conf_bits_msb(),
VERILOG_PORT_INPUT);
/* Dump ports only visible during formal verification*/
if (0 < rr_sb.get_sb_num_conf_bits()) {
if (0 < rr_gsb.get_sb_num_conf_bits()) {
fprintf(fp, "\n");
fprintf(fp, "//----- SRAM Ports for formal verification -----\n");
fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag);
fprintf(fp, ",\n");
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
rr_sb.get_sb_conf_bits_lsb(),
rr_sb.get_sb_conf_bits_msb(),
rr_gsb.get_sb_conf_bits_lsb(),
rr_gsb.get_sb_conf_bits_msb(),
VERILOG_PORT_INPUT);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
@ -2227,34 +2228,34 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
/* Local wires for memory configurations */
dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info,
rr_sb.get_sb_conf_bits_lsb(),
rr_sb.get_sb_conf_bits_msb());
rr_gsb.get_sb_conf_bits_lsb(),
rr_gsb.get_sb_conf_bits_msb());
/* Call submodules */
int cur_sram_lsb = cur_num_sram;
int cur_sram_msb = cur_num_sram;
for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) {
for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
Side side_manager(side);
fprintf(fp, "//----- %s side Submodule -----\n",
side_manager.c_str());
/* Get the channel width on this side, if it is zero, we return */
if (0 == rr_sb.get_chan_width(side_manager.get_side())) {
if (0 == rr_gsb.get_chan_width(side_manager.get_side())) {
fprintf(fp, "//----- %s side has zero channel width, module dump skipped -----\n",
side_manager.c_str());
continue;
}
/* get segment ids */
std::vector<size_t> seg_ids = rr_sb.get_chan(side_manager.get_side()).get_segment_ids();
std::vector<size_t> seg_ids = rr_gsb.get_chan(side_manager.get_side()).get_segment_ids();
for (size_t iseg = 0; iseg < seg_ids.size(); ++iseg) {
fprintf(fp, "//----- %s side Submodule with Segment id: %lu -----\n",
side_manager.c_str(), seg_ids[iseg]);
/* Count the number of configuration bits to be consumed by this Switch block */
int side_num_conf_bits = count_verilog_switch_box_side_conf_bits(cur_sram_orgz_info, rr_sb, side_manager.get_side(), seg_ids[iseg]);
int side_num_conf_bits = count_verilog_switch_box_side_conf_bits(cur_sram_orgz_info, rr_gsb, side_manager.get_side(), seg_ids[iseg]);
/* Count the number of reserved configuration bits to be consumed by this Switch block */
int side_num_reserved_conf_bits = count_verilog_switch_box_side_reserved_conf_bits(cur_sram_orgz_info, rr_sb, side_manager.get_side(), seg_ids[iseg]);
int side_num_reserved_conf_bits = count_verilog_switch_box_side_reserved_conf_bits(cur_sram_orgz_info, rr_gsb, side_manager.get_side(), seg_ids[iseg]);
/* Cache the sram counter */
cur_sram_msb = cur_sram_lsb + side_num_conf_bits - 1;
@ -2262,14 +2263,14 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
/* Instanciate the subckt*/
fprintf(fp,
"%s %s ( \n",
rr_sb.gen_sb_verilog_side_module_name(side_manager.get_side(), seg_ids[iseg]),
rr_sb.gen_sb_verilog_side_instance_name(side_manager.get_side(), seg_ids[iseg]));
rr_gsb.gen_sb_verilog_side_module_name(side_manager.get_side(), seg_ids[iseg]),
rr_gsb.gen_sb_verilog_side_instance_name(side_manager.get_side(), seg_ids[iseg]));
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
fprintf(fp, ",\n");
}
dump_verilog_routing_switch_box_unique_side_subckt_portmap(fp, rr_sb, side_manager.get_side(), seg_ids[iseg], FALSE);
dump_verilog_routing_switch_box_unique_side_subckt_portmap(fp, rr_gsb, side_manager.get_side(), seg_ids[iseg], FALSE);
/* Put down configuration port */
/* output of each configuration bit */
@ -2311,7 +2312,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
fprintf(fp, "endmodule\n");
/* Comment lines */
fprintf(fp, "//----- END Verilog Module of Switch Box[%lu][%lu] -----\n\n", rr_sb.get_sb_x(), rr_sb.get_sb_y());
fprintf(fp, "//----- END Verilog Module of Switch Box[%lu][%lu] -----\n\n", rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
/* Close file handler */
fclose(fp);
@ -2363,7 +2364,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
static
void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir, char* subckt_dir,
RRGSB& rr_sb) {
const RRGSB& rr_sb) {
FILE* fp = NULL;
char* fname = NULL;
@ -2374,61 +2375,62 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or
/* Estimate the sram_verilog_model->cnt */
int cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info);
int esti_sram_cnt = cur_num_sram + num_conf_bits;
rr_sb.set_sb_num_reserved_conf_bits(num_reserved_conf_bits);
rr_sb.set_sb_conf_bits_lsb(cur_num_sram);
rr_sb.set_sb_conf_bits_msb(cur_num_sram + num_conf_bits - 1);
RRGSB rr_gsb = rr_sb; /* IMPORTANT: this copy will be removed when the config ports are initialized when created!!! */
rr_gsb.set_sb_num_reserved_conf_bits(num_reserved_conf_bits);
rr_gsb.set_sb_conf_bits_lsb(cur_num_sram);
rr_gsb.set_sb_conf_bits_msb(cur_num_sram + num_conf_bits - 1);
/* Create file handler */
fp = verilog_create_one_subckt_file(subckt_dir, "Unique Switch Block ",
sb_verilog_file_name_prefix, rr_sb.get_sb_x(), rr_sb.get_sb_y(), &fname);
sb_verilog_file_name_prefix, rr_gsb.get_sb_x(), rr_gsb.get_sb_y(), &fname);
/* Print preprocessing flags */
verilog_include_defines_preproc_file(fp, verilog_dir);
/* Comment lines */
fprintf(fp, "//----- Verilog Module of Unique Switch Box[%lu][%lu] -----\n", rr_sb.get_sb_x(), rr_sb.get_sb_y());
fprintf(fp, "//----- Verilog Module of Unique Switch Box[%lu][%lu] -----\n", rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
/* Print the definition of subckt*/
fprintf(fp, "module %s ( \n", rr_sb.gen_sb_verilog_module_name());
fprintf(fp, "module %s ( \n", rr_gsb.gen_sb_verilog_module_name());
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
fprintf(fp, ",\n");
}
for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) {
for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
Side side_manager(side);
/* Print ports */
fprintf(fp, "//----- Inputs/outputs of %s side -----\n", side_manager.c_str());
DeviceCoordinator port_coordinator = rr_sb.get_side_block_coordinator(side_manager.get_side());
DeviceCoordinator port_coordinator = rr_gsb.get_side_block_coordinator(side_manager.get_side());
for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) {
switch (rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)) {
for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) {
switch (rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) {
case OUT_PORT:
fprintf(fp, " output %s,\n",
gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack),
gen_verilog_routing_channel_one_pin_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack),
port_coordinator.get_x(), port_coordinator.get_y(), itrack,
rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)));
rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)));
break;
case IN_PORT:
fprintf(fp, " input %s,\n",
gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack),
gen_verilog_routing_channel_one_pin_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack),
port_coordinator.get_x(), port_coordinator.get_y(), itrack,
rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)));
rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)));
break;
default:
vpr_printf(TIO_MESSAGE_ERROR,
"(File: %s [LINE%d]) Invalid direction of chan[%d][%d]_track[%d]!\n",
__FILE__, __LINE__, rr_sb.get_sb_x(), rr_sb.get_sb_y(), itrack);
__FILE__, __LINE__, rr_gsb.get_sb_x(), rr_gsb.get_sb_y(), itrack);
exit(1);
}
}
/* Dump OPINs of adjacent CLBs */
for (size_t inode = 0; inode < rr_sb.get_num_opin_nodes(side_manager.get_side()); ++inode) {
for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) {
fprintf(fp, " ");
dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an input of a SB */
rr_sb.get_opin_node(side_manager.get_side(), inode)->ptc_num,
rr_sb.get_opin_node_grid_side(side_manager.get_side(), inode),
rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow,
rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow,
rr_gsb.get_opin_node(side_manager.get_side(), inode)->ptc_num,
rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode),
rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow,
rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow,
TRUE); /* Dump the direction of the port ! */
}
}
@ -2436,27 +2438,27 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or
/* Put down configuration port */
/* output of each configuration bit */
/* Reserved sram ports */
if (0 < rr_sb.get_sb_num_reserved_conf_bits()) {
if (0 < rr_gsb.get_sb_num_reserved_conf_bits()) {
dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info,
rr_sb.get_sb_reserved_conf_bits_lsb(),
rr_sb.get_sb_reserved_conf_bits_msb(),
rr_gsb.get_sb_reserved_conf_bits_lsb(),
rr_gsb.get_sb_reserved_conf_bits_msb(),
VERILOG_PORT_INPUT);
fprintf(fp, ",\n");
}
/* Normal sram ports */
dump_verilog_sram_ports(fp, cur_sram_orgz_info,
rr_sb.get_sb_conf_bits_lsb(),
rr_sb.get_sb_conf_bits_msb(),
rr_gsb.get_sb_conf_bits_lsb(),
rr_gsb.get_sb_conf_bits_msb(),
VERILOG_PORT_INPUT);
/* Dump ports only visible during formal verification*/
if (0 < rr_sb.get_sb_num_conf_bits()) {
if (0 < rr_gsb.get_sb_num_conf_bits()) {
fprintf(fp, "\n");
fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag);
fprintf(fp, ",\n");
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
rr_sb.get_sb_conf_bits_lsb(),
rr_sb.get_sb_conf_bits_msb(),
rr_gsb.get_sb_conf_bits_lsb(),
rr_gsb.get_sb_conf_bits_msb(),
VERILOG_PORT_OUTPUT);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
@ -2465,22 +2467,22 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or
/* Local wires for memory configurations */
dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info,
rr_sb.get_sb_conf_bits_lsb(),
rr_sb.get_sb_conf_bits_msb());
rr_gsb.get_sb_conf_bits_lsb(),
rr_gsb.get_sb_conf_bits_msb());
/* Put down all the multiplexers */
for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) {
for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
Side side_manager(side);
fprintf(fp, "//----- %s side Multiplexers -----\n",
side_manager.c_str());
for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) {
assert((CHANX == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type)
||(CHANY == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type));
for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) {
assert((CHANX == rr_gsb.get_chan_node(side_manager.get_side(), itrack)->type)
||(CHANY == rr_gsb.get_chan_node(side_manager.get_side(), itrack)->type));
/* We care INC_DIRECTION tracks at this side*/
if (OUT_PORT == rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)) {
if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) {
dump_verilog_unique_switch_box_interc(cur_sram_orgz_info, fp, rr_sb,
side_manager.get_side(),
rr_sb.get_chan_node(side_manager.get_side(), itrack));
rr_gsb.get_chan_node(side_manager.get_side(), itrack));
}
}
}
@ -2488,7 +2490,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or
fprintf(fp, "endmodule\n");
/* Comment lines */
fprintf(fp, "//----- END Verilog Module of Switch Box[%lu][%lu] -----\n\n", rr_sb.get_sb_x(), rr_sb.get_sb_y());
fprintf(fp, "//----- END Verilog Module of Switch Box[%lu][%lu] -----\n\n", rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
/* Check */
assert(esti_sram_cnt == get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info));
@ -2760,7 +2762,7 @@ int count_verilog_connection_box_interc_reserved_conf_bits(t_sram_orgz_info* cur
int count_verilog_connection_box_one_side_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
RRGSB& rr_gsb, enum e_side cb_side) {
const RRGSB& rr_gsb, enum e_side cb_side) {
int num_conf_bits = 0;
for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_side); ++inode) {
num_conf_bits += count_verilog_connection_box_interc_conf_bits(cur_sram_orgz_info, rr_gsb.get_ipin_node(cb_side, inode));
@ -2783,7 +2785,7 @@ int count_verilog_connection_box_one_side_conf_bits(t_sram_orgz_info* cur_sram_o
}
int count_verilog_connection_box_one_side_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
RRGSB& rr_gsb, enum e_side cb_side) {
const RRGSB& rr_gsb, enum e_side cb_side) {
int num_reserved_conf_bits = 0;
for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_side); ++inode) {
@ -2816,7 +2818,7 @@ int count_verilog_connection_box_one_side_reserved_conf_bits(t_sram_orgz_info* c
/* SRC rr_node is the IPIN of a grid.*/
static
void dump_verilog_connection_box_short_interc(FILE* fp,
RRGSB& rr_gsb, t_rr_type cb_type,
const RRGSB& rr_gsb, t_rr_type cb_type,
t_rr_node* src_rr_node) {
t_rr_node* drive_rr_node = NULL;
int iedge, check_flag;
@ -2958,7 +2960,7 @@ void dump_verilog_connection_box_short_interc(FILE* fp,
static
void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
RRGSB& rr_gsb, t_rr_type cb_type,
const RRGSB& rr_gsb, t_rr_type cb_type,
t_rr_node* src_rr_node) {
int mux_size, cur_num_sram, input_cnt = 0;
t_rr_node** drive_rr_nodes = NULL;
@ -3414,7 +3416,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
static
void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
RRGSB& rr_gsb, t_rr_type cb_type,
const RRGSB& rr_gsb, t_rr_type cb_type,
t_rr_node* src_rr_node) {
/* Check the file handler*/
if (NULL == fp) {
@ -3463,7 +3465,7 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
/* Count the number of configuration bits of a connection box */
int count_verilog_connection_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
RRGSB& rr_gsb, t_rr_type cb_type) {
const RRGSB& rr_gsb, t_rr_type cb_type) {
int num_conf_bits = 0;
std::vector<enum e_side> cb_sides = rr_gsb.get_cb_ipin_sides(cb_type);
@ -3507,7 +3509,7 @@ int count_verilog_connection_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
/* Count the number of reserved configuration bits of a connection box */
int count_verilog_connection_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
RRGSB& rr_gsb, t_rr_type cb_type) {
const RRGSB& rr_gsb, t_rr_type cb_type) {
int num_reserved_conf_bits = 0;
std::vector<enum e_side> cb_sides = rr_gsb.get_cb_ipin_sides(cb_type);
@ -3580,11 +3582,13 @@ int count_verilog_connection_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_o
static
void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir, char* subckt_dir,
RRGSB& rr_gsb, t_rr_type cb_type) {
const RRGSB& rr_cb, t_rr_type cb_type) {
FILE* fp = NULL;
char* fname = NULL;
int cur_num_sram, num_conf_bits, num_reserved_conf_bits, esti_sram_cnt;
RRGSB rr_gsb = rr_cb; /* IMPORTANT: this copy will be removed when the config ports are initialized when created!!! */
/* Count the number of configuration bits */
/* Count the number of configuration bits to be consumed by this Switch block */
num_conf_bits = count_verilog_connection_box_conf_bits(cur_sram_orgz_info, rr_gsb, cb_type);
@ -4025,7 +4029,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
Side side_manager(side);
for (size_t iseg = 0; iseg < device_rr_gsb.get_num_segments(); ++iseg) {
for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_submodule(side_manager.get_side(), iseg); ++isb) {
RRGSB unique_mirror = device_rr_gsb.get_sb_unique_submodule(isb, side_manager.get_side(), iseg);
const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_submodule(isb, side_manager.get_side(), iseg);
size_t seg_id = device_rr_gsb.get_segment_id(iseg);
dump_verilog_routing_switch_box_unique_side_module(cur_sram_orgz_info, verilog_dir, subckt_dir, isb, seg_id, unique_mirror, side_manager.get_side());
}
@ -4034,7 +4038,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
/* Output unique modules */
for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
RRGSB unique_mirror = device_rr_gsb.get_sb_unique_module(isb);
const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb);
dump_verilog_routing_switch_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror);
}
@ -4044,7 +4048,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
DeviceCoordinator sb_range = device_rr_gsb.get_gsb_range();
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
RRGSB rr_sb = device_rr_gsb.get_gsb(ix, iy);
const RRGSB& rr_sb = device_rr_gsb.get_gsb(ix, iy);
update_routing_switch_box_conf_bits(cur_sram_orgz_info, rr_sb);
}
}
@ -4075,7 +4079,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
for (int iy = 0; iy < (ny + 1); iy++) {
for (int ix = 1; ix < (nx + 1); ix++) {
for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) {
RRGSB unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb);
const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb);
dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, CHANX);
}
}
@ -4084,7 +4088,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
* updating the conf bits should follow a tile organization: CLB, SB and CBX, CBY */
for (size_t ix = 0; ix < cb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < cb_range.get_y(); ++iy) {
RRGSB rr_gsb = device_rr_gsb.get_gsb(ix, iy);
const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
update_routing_connection_box_conf_bits(cur_sram_orgz_info, rr_gsb, CHANX);
}
}
@ -4093,7 +4097,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
for (int ix = 0; ix < (nx + 1); ix++) {
for (int iy = 1; iy < (ny + 1); iy++) {
for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) {
RRGSB unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb);
const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb);
dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, CHANY);
}
}
@ -4101,7 +4105,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
for (size_t ix = 0; ix < cb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < cb_range.get_y(); ++iy) {
RRGSB rr_gsb = device_rr_gsb.get_gsb(ix, iy);
const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
update_routing_connection_box_conf_bits(cur_sram_orgz_info, rr_gsb, CHANY);
}
}

8
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h
View File

@ -90,27 +90,27 @@ int count_verilog_connection_box_interc_conf_bits(t_sram_orgz_info* cur_sram_org
t_rr_node* cur_rr_node);
int count_verilog_connection_box_one_side_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
RRGSB& rr_gsb, enum e_side cb_side);
const RRGSB& rr_gsb, enum e_side cb_side);
int count_verilog_connection_box_interc_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
t_rr_node* cur_rr_node);
int count_verilog_connection_box_one_side_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
RRGSB& rr_gsb, enum e_side cb_side);
const RRGSB& rr_gsb, enum e_side cb_side);
int count_verilog_connection_box_one_side_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
int num_ipin_rr_nodes,
t_rr_node** ipin_rr_node);
int count_verilog_connection_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
RRGSB& rr_gsb, t_rr_type cb_type);
const RRGSB& rr_gsb, t_rr_type cb_type);
int count_verilog_connection_box_one_side_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
int num_ipin_rr_nodes,
t_rr_node** ipin_rr_node);
int count_verilog_connection_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
RRGSB& rr_gsb, t_rr_type cb_type);
const RRGSB& rr_gsb, t_rr_type cb_type);
int count_verilog_connection_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
t_cb* cur_cb_info);

368
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c
View File

@ -52,6 +52,7 @@ struct s_sdc_opts {
boolean constrain_routing_channels;
boolean break_loops;
boolean break_loops_mux;
boolean compact_routing_hierarchy; /* This option is going to be deprecated when new data structure RRGSB replaces the old data structures */
};
static
@ -344,13 +345,57 @@ void verilog_generate_sdc_break_loop_sb(FILE* fp,
return;
}
static
void verilog_generate_sdc_break_loop_sb(FILE* fp,
DeviceRRGSB& LL_device_rr_gsb) {
/* Check the file handler */
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,
"(FILE:%s,LINE[%d])Invalid file handler for SDC generation",
__FILE__, __LINE__);
exit(1);
}
/* Get the range of SB array */
DeviceCoordinator sb_range = LL_device_rr_gsb.get_gsb_range();
/* Go for each SB */
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
Side side_manager(side);
for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) {
t_rr_node* chan_rr_node = rr_gsb.get_chan_node(side_manager.get_side(), itrack);
assert((CHANX == chan_rr_node->type)
||(CHANY == chan_rr_node->type));
/* We only care the output port and it should indicate a SB mux */
if ( (OUT_PORT != rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack))
|| (false != rr_gsb.is_sb_node_imply_short_connection(chan_rr_node))) {
continue;
}
/* Bypass if we have only 1 driving node */
if (1 == chan_rr_node->num_drive_rr_nodes) {
continue;
}
/* Disable timing here */
set_disable_timing_one_sb_output(fp, rr_gsb,
chan_rr_node);
}
}
}
}
return;
}
static
void verilog_generate_sdc_break_loops(t_sram_orgz_info* cur_sram_orgz_info,
t_sdc_opts sdc_opts,
int LL_nx, int LL_ny,
int num_switch,
t_switch_inf* switches,
t_spice* spice,
t_spice* spice, DeviceRRGSB& LL_device_rr_gsb,
t_det_routing_arch* routing_arch) {
FILE* fp = NULL;
char* fname = my_strcat(sdc_opts.sdc_dir, sdc_break_loop_file_name);
@ -379,7 +424,11 @@ void verilog_generate_sdc_break_loops(t_sram_orgz_info* cur_sram_orgz_info,
}
/* 3. Break loops from any SB output */
verilog_generate_sdc_break_loop_sb(fp, LL_nx, LL_ny);
if (TRUE == sdc_opts.compact_routing_hierarchy) {
verilog_generate_sdc_break_loop_sb(fp, LL_device_rr_gsb);
} else {
verilog_generate_sdc_break_loop_sb(fp, LL_nx, LL_ny);
}
/* Close the file*/
fclose(fp);
@ -435,6 +484,52 @@ void verilog_generate_sdc_constrain_one_sb_path(FILE* fp,
return;
}
/* Constrain a path within a Switch block,
* If this indicates a metal wire, we constraint to be 0 delay
*/
static
void verilog_generate_sdc_constrain_one_sb_path(FILE* fp,
const RRGSB& rr_gsb,
t_rr_node* src_rr_node,
t_rr_node* des_rr_node,
float tmax) {
/* Check the file handler */
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,
"(FILE:%s,LINE[%d])Invalid file handler for SDC generation",
__FILE__, __LINE__);
exit(1);
}
/* Check */
assert ((OPIN == src_rr_node->type)
||(CHANX == src_rr_node->type)
||(CHANY == src_rr_node->type));
assert ((CHANX == des_rr_node->type)
||(CHANY == des_rr_node->type));
fprintf(fp, "set_max_delay");
fprintf(fp, " -from ");
fprintf(fp, "%s/",
rr_gsb.gen_sb_verilog_instance_name());
dump_verilog_one_sb_routing_pin(fp, rr_gsb, src_rr_node);
fprintf(fp, " -to ");
fprintf(fp, "%s/",
rr_gsb.gen_sb_verilog_instance_name());
dump_verilog_one_sb_chan_pin(fp, rr_gsb, des_rr_node, OUT_PORT);
/* If src_node == des_node, this is a metal wire */
fprintf(fp, " %.2g", tmax);
fprintf(fp, "\n");
return;
}
static
void verilog_generate_sdc_constrain_one_sb_mux(FILE* fp,
t_sb* cur_sb_info,
@ -468,6 +563,37 @@ void verilog_generate_sdc_constrain_one_sb_mux(FILE* fp,
return;
}
static
void verilog_generate_sdc_constrain_one_sb_mux(FILE* fp,
const RRGSB& rr_gsb,
t_rr_node* wire_rr_node) {
/* Check the file handler */
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,
"(FILE:%s,LINE[%d])Invalid file handler for SDC generation",
__FILE__, __LINE__);
exit(1);
}
assert( ( CHANX == wire_rr_node->type )
|| ( CHANY == wire_rr_node->type ));
/* Find the starting points */
for (int iedge = 0; iedge < wire_rr_node->num_drive_rr_nodes; iedge++) {
/* Get the switch delay */
int switch_id = wire_rr_node->drive_switches[iedge];
float switch_delay = get_switch_sdc_tmax (&(switch_inf[switch_id]));
/* Constrain a path */
verilog_generate_sdc_constrain_one_sb_path(fp, rr_gsb,
wire_rr_node->drive_rr_nodes[iedge],
wire_rr_node,
switch_delay);
}
return;
}
/* Constrain a path within a Switch block,
* If this indicates a metal wire, we constraint to be 0 delay
*/
@ -522,6 +648,123 @@ void verilog_generate_sdc_constrain_one_cb_path(FILE* fp,
return;
}
/* Constrain a path within a Switch block,
* If this indicates a metal wire, we constraint to be 0 delay
*/
static
void verilog_generate_sdc_constrain_one_cb_path(FILE* fp,
const RRGSB& rr_gsb, t_rr_type cb_type,
t_rr_node* src_rr_node,
t_rr_node* des_rr_node,
int des_rr_node_grid_side,
float tmax) {
/* Check the file handler */
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,
"(FILE:%s,LINE[%d])Invalid file handler for SDC generation",
__FILE__, __LINE__);
exit(1);
}
/* Check */
assert ((INC_DIRECTION == src_rr_node->direction)
||(DEC_DIRECTION == src_rr_node->direction));
assert ((CHANX == src_rr_node->type)
||(CHANY == src_rr_node->type));
assert (IPIN == des_rr_node->type);
fprintf(fp, "set_max_delay");
fprintf(fp, " -from ");
fprintf(fp, "%s/",
rr_gsb.gen_cb_verilog_instance_name(cb_type));
fprintf(fp, "%s",
rr_gsb.gen_cb_verilog_routing_track_name(cb_type, src_rr_node->ptc_num));
fprintf(fp, " -to ");
fprintf(fp, "%s/",
rr_gsb.gen_cb_verilog_instance_name(cb_type));
dump_verilog_grid_side_pin_with_given_index(fp, IPIN, /* This is an output of a connection box */
des_rr_node->ptc_num,
des_rr_node_grid_side,
des_rr_node->xlow,
des_rr_node->ylow,
FALSE);
/* If src_node == des_node, this is a metal wire */
fprintf(fp, " %.2g", tmax);
fprintf(fp, "\n");
return;
}
/* Constrain the inputs and outputs of SBs, with the Switch delays */
static
void verilog_generate_sdc_constrain_sbs(t_sdc_opts sdc_opts,
DeviceRRGSB& LL_device_rr_gsb) {
FILE* fp = NULL;
char* fname = my_strcat(sdc_opts.sdc_dir, sdc_constrain_sb_file_name);
vpr_printf(TIO_MESSAGE_INFO,
"Generating SDC for constraining Switch Blocks in P&R flow: %s ...\n",
fname);
/* Print the muxes netlist*/
fp = fopen(fname, "w");
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,
"(FILE:%s,LINE[%d])Failure in create SDC constraints %s",
__FILE__, __LINE__, fname);
exit(1);
}
/* Generate the descriptions*/
dump_verilog_sdc_file_header(fp, "Constrain Switch Blocks for PnR");
/* Get the range of SB array */
DeviceCoordinator sb_range = LL_device_rr_gsb.get_gsb_range();
/* Go for each SB */
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
Side side_manager(side);
for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) {
t_rr_node* chan_rr_node = rr_gsb.get_chan_node(side_manager.get_side(), itrack);
assert((CHANX == chan_rr_node->type)
||(CHANY == chan_rr_node->type));
/* We only care the output port and it should indicate a SB mux */
if (OUT_PORT != rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) {
continue;
}
/* Constrain thru wires */
if (false != rr_gsb.is_sb_node_imply_short_connection(chan_rr_node)) {
/* Set the max, min delay to 0? */
verilog_generate_sdc_constrain_one_sb_path(fp, rr_gsb,
chan_rr_node,
chan_rr_node,
0.);
continue;
}
/* This is a MUX, constrain all the paths from an input to an output */
verilog_generate_sdc_constrain_one_sb_mux(fp, rr_gsb,
chan_rr_node);
}
}
}
}
/* Close the file*/
fclose(fp);
/* Free strings */
my_free(fname);
return;
}
/* Constrain the inputs and outputs of SBs, with the Switch delays */
static
@ -634,6 +877,45 @@ void verilog_generate_sdc_constrain_one_cb(FILE* fp,
return;
}
static
void verilog_generate_sdc_constrain_one_cb(FILE* fp,
const RRGSB& rr_gsb, t_rr_type cb_type) {
/* Check the file handler */
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,
"(FILE:%s,LINE[%d])Invalid file handler for SDC generation",
__FILE__, __LINE__);
exit(1);
}
/* Print the ports of grids*/
/* only check ipin_rr_nodes of cur_cb_info */
std::vector<enum e_side> cb_sides = rr_gsb.get_cb_ipin_sides(cb_type);
for (size_t side = 0; side < cb_sides.size(); ++side) {
enum e_side cb_ipin_side = cb_sides[side];
Side side_manager(cb_ipin_side);
for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) {
t_rr_node* cur_ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode);
for (int iedge = 0; iedge < cur_ipin_node->num_drive_rr_nodes; iedge++) {
/* Get the switch delay */
int switch_id = cur_ipin_node->drive_switches[iedge];
float switch_delay = get_switch_sdc_tmax (&(switch_inf[switch_id]));
/* Print each INPUT Pins of a grid */
verilog_generate_sdc_constrain_one_cb_path(fp, rr_gsb, cb_type,
cur_ipin_node->drive_rr_nodes[iedge],
cur_ipin_node,
rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode),
switch_delay);
}
}
}
return;
}
/* Constrain the inputs and outputs of Connection Blocks, with the Switch delays */
static
void verilog_generate_sdc_constrain_cbs(t_sdc_opts sdc_opts,
@ -686,6 +968,59 @@ void verilog_generate_sdc_constrain_cbs(t_sdc_opts sdc_opts,
return;
}
/* Constrain the inputs and outputs of Connection Blocks, with the Switch delays */
static
void verilog_generate_sdc_constrain_cbs(t_sdc_opts sdc_opts, int LL_nx, int LL_ny,
DeviceRRGSB& LL_device_rr_gsb) {
FILE* fp = NULL;
char* fname = my_strcat(sdc_opts.sdc_dir, sdc_constrain_cb_file_name);
vpr_printf(TIO_MESSAGE_INFO,
"Generating SDC for constraining Connection Blocks in P&R flow: %s ...\n",
fname);
/* Print the muxes netlist*/
fp = fopen(fname, "w");
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,
"(FILE:%s,LINE[%d])Failure in create SDC constraints %s",
__FILE__, __LINE__, fname);
exit(1);
}
/* Generate the descriptions*/
dump_verilog_sdc_file_header(fp, "Constrain Connection Blocks for PnR");
/* Connection Boxes */
/* X - channels [1...nx][0..ny]*/
for (int iy = 0; iy < (LL_ny + 1); ++iy) {
for (int ix = 1; ix < (LL_nx + 1); ++ix) {
const RRGSB& rr_gsb = LL_device_rr_gsb.get_gsb(ix, iy);
if ( (TRUE == is_cb_exist(CHANX, ix, iy))
&&(true == rr_gsb.is_cb_exist(CHANX))) {
verilog_generate_sdc_constrain_one_cb(fp, rr_gsb, CHANX);
}
}
}
/* Y - channels [1...ny][0..nx]*/
for (int ix = 0; ix < (LL_nx + 1); ++ix) {
for (int iy = 1; iy < (LL_ny + 1); ++iy) {
const RRGSB& rr_gsb = LL_device_rr_gsb.get_gsb(ix, iy);
if ((TRUE == is_cb_exist(CHANY, ix, iy))
&&(true == rr_gsb.is_cb_exist(CHANY))) {
verilog_generate_sdc_constrain_one_cb(fp, rr_gsb, CHANY);
}
}
}
/* Close the file*/
fclose(fp);
/* Free strings */
my_free(fname);
return;
}
static
void verilog_generate_sdc_constrain_one_chan(FILE* fp,
t_rr_type chan_type,
@ -1016,7 +1351,7 @@ void verilog_generate_sdc_disable_unused_sbs_muxs(FILE* fp) {
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
RRGSB rr_sb = device_rr_gsb.get_gsb(ix, iy);
const RRGSB& rr_sb = device_rr_gsb.get_gsb(ix, iy);
/* Print comments */
fprintf(fp,
"########################################################\n");
@ -2175,7 +2510,7 @@ void verilog_generate_sdc_pnr(t_sram_orgz_info* cur_sram_orgz_info,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices,
t_rr_indexed_data* LL_rr_indexed_data,
int LL_nx, int LL_ny,
int LL_nx, int LL_ny, DeviceRRGSB& LL_device_rr_gsb,
boolean compact_routing_hierarchy) {
t_sdc_opts sdc_opts;
@ -2187,6 +2522,7 @@ void verilog_generate_sdc_pnr(t_sram_orgz_info* cur_sram_orgz_info,
sdc_opts.constrain_cbs = TRUE;
sdc_opts.break_loops = TRUE;
sdc_opts.break_loops_mux = FALSE; /* By default, we turn it off to avoid a overkill */
sdc_opts.compact_routing_hierarchy = compact_routing_hierarchy; /* By default, we turn it off to avoid a overkill */
/* Part 1. Constrain clock cycles */
verilog_generate_sdc_clock_period(sdc_opts, pow(10,9)*arch.spice->spice_params.stimulate_params.vpr_crit_path_delay);
@ -2196,20 +2532,28 @@ void verilog_generate_sdc_pnr(t_sram_orgz_info* cur_sram_orgz_info,
verilog_generate_sdc_break_loops(cur_sram_orgz_info, sdc_opts,
LL_nx, LL_ny,
routing_arch->num_switch, switch_inf,
arch.spice,
arch.spice, LL_device_rr_gsb,
routing_arch);
}
/* Part 3. Output routing constraints for Switch Blocks */
if (TRUE == sdc_opts.constrain_sbs) {
verilog_generate_sdc_constrain_sbs(sdc_opts,
LL_nx, LL_ny);
if (TRUE == compact_routing_hierarchy) {
verilog_generate_sdc_constrain_sbs(sdc_opts, LL_device_rr_gsb);
} else {
verilog_generate_sdc_constrain_sbs(sdc_opts,
LL_nx, LL_ny);
}
}
/* Part 4. Output routing constraints for Connection Blocks */
if (TRUE == sdc_opts.constrain_cbs) {
verilog_generate_sdc_constrain_cbs(sdc_opts,
LL_nx, LL_ny);
if (TRUE == compact_routing_hierarchy) {
verilog_generate_sdc_constrain_cbs(sdc_opts, LL_nx, LL_ny, LL_device_rr_gsb);
} else {
verilog_generate_sdc_constrain_cbs(sdc_opts,
LL_nx, LL_ny);
}
}
/* Part 5. Output routing constraints for Connection Blocks */
@ -2236,7 +2580,7 @@ void verilog_generate_sdc_analysis(t_sram_orgz_info* cur_sram_orgz_info,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices,
int LL_nx, int LL_ny, t_grid_tile** LL_grid,
t_block* LL_block,
t_block* LL_block, DeviceRRGSB& LL_device_rr_gsb,
boolean compact_routing_hierarchy) {
FILE* fp = NULL;
char* fname = my_strcat(sdc_dir, sdc_analysis_file_name);
@ -2278,8 +2622,8 @@ void verilog_generate_sdc_analysis(t_sram_orgz_info* cur_sram_orgz_info,
/* Apply to Connection blocks */
if (TRUE == compact_routing_hierarchy) {
verilog_generate_sdc_disable_unused_cbs(fp, LL_nx, LL_ny, device_rr_gsb);
verilog_generate_sdc_disable_unused_cbs_muxs(fp, LL_nx, LL_ny, device_rr_gsb);
verilog_generate_sdc_disable_unused_cbs(fp, LL_nx, LL_ny, LL_device_rr_gsb);
verilog_generate_sdc_disable_unused_cbs_muxs(fp, LL_nx, LL_ny, LL_device_rr_gsb);
} else {
verilog_generate_sdc_disable_unused_cbs(fp, LL_nx, LL_ny);
verilog_generate_sdc_disable_unused_cbs_muxs(fp, LL_nx, LL_ny);

4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.h
View File

@ -8,7 +8,7 @@ void verilog_generate_sdc_pnr(t_sram_orgz_info* cur_sram_orgz_info,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices,
t_rr_indexed_data* LL_rr_indexed_data,
int LL_nx, int LL_ny,
int LL_nx, int LL_ny, DeviceRRGSB& LL_device_rr_gsb,
boolean compact_routing_hierarchy);
void verilog_generate_sdc_analysis(t_sram_orgz_info* cur_sram_orgz_info,
@ -17,7 +17,7 @@ void verilog_generate_sdc_analysis(t_sram_orgz_info* cur_sram_orgz_info,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices,
int LL_nx, int LL_ny, t_grid_tile** LL_grid,
t_block* LL_block,
t_block* LL_block, DeviceRRGSB& LL_device_rr_gsb,
boolean compact_routing_hierarchy);
void dump_sdc_one_clb_muxes(FILE* fp,

10
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c
View File

@ -60,7 +60,7 @@ void dump_verilog_sdc_file_header(FILE* fp,
}
void dump_verilog_one_sb_chan_pin(FILE* fp,
RRGSB& rr_sb,
const RRGSB& rr_sb,
t_rr_node* cur_rr_node,
enum PORTS port_type) {
int track_idx;
@ -135,7 +135,7 @@ void dump_verilog_one_sb_chan_pin(FILE* fp,
/* Output the pin name of a routing wire in a SB */
void dump_verilog_one_sb_routing_pin(FILE* fp,
RRGSB& rr_sb,
const RRGSB& rr_sb,
t_rr_node* cur_rr_node) {
int side;
@ -398,7 +398,7 @@ DeviceCoordinator get_chan_node_ending_sb_coordinator(t_rr_node* src_rr_node,
}
DeviceCoordinator sb_coordinator(next_sb_x, next_sb_y);
RRGSB rr_sb = device_rr_gsb.get_gsb(sb_coordinator);
const RRGSB& rr_sb = device_rr_gsb.get_gsb(sb_coordinator);
/* Double check if src_rr_node is in the list */
enum e_side side;
int index;
@ -552,7 +552,7 @@ t_sb* get_chan_rr_node_ending_sb(t_rr_node* src_rr_node,
/* Restore the disabled timing for the sb wire */
void restore_disable_timing_one_sb_output(FILE* fp,
RRGSB& rr_sb,
const RRGSB& rr_sb,
t_rr_node* wire_rr_node) {
/* Check the file handler */
if (NULL == fp) {
@ -604,7 +604,7 @@ void restore_disable_timing_one_sb_output(FILE* fp,
/* Restore the disabled timing for the sb wire */
void set_disable_timing_one_sb_output(FILE* fp,
RRGSB& rr_sb,
const RRGSB& rr_sb,
t_rr_node* wire_rr_node) {
/* Check the file handler */
if (NULL == fp) {

8
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.h
View File

@ -9,7 +9,7 @@ void dump_verilog_sdc_file_header(FILE* fp,
char* usage);
void dump_verilog_one_sb_chan_pin(FILE* fp,
RRGSB& rr_sb,
const RRGSB& rr_sb,
t_rr_node* cur_rr_node,
enum PORTS port_type);
@ -19,7 +19,7 @@ void dump_verilog_one_sb_chan_pin(FILE* fp,
enum PORTS port_type);
void dump_verilog_one_sb_routing_pin(FILE* fp,
RRGSB& rr_sb,
const RRGSB& rr_sb,
t_rr_node* cur_rr_node);
void dump_verilog_one_sb_routing_pin(FILE* fp,
@ -36,7 +36,7 @@ t_sb* get_chan_rr_node_ending_sb(t_rr_node* src_rr_node,
t_rr_node* end_rr_node);
void restore_disable_timing_one_sb_output(FILE* fp,
RRGSB& rr_sb,
const RRGSB& rr_sb,
t_rr_node* wire_rr_node);
void restore_disable_timing_one_sb_output(FILE* fp,
@ -44,7 +44,7 @@ void restore_disable_timing_one_sb_output(FILE* fp,
t_rr_node* wire_rr_node);
void set_disable_timing_one_sb_output(FILE* fp,
RRGSB& rr_sb,
const RRGSB& rr_sb,
t_rr_node* wire_rr_node);
void set_disable_timing_one_sb_output(FILE* fp,