riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

bugs fixed for shift register benchmark

This commit is contained in:
Aur??Lien ALACCHI 2018-11-26 16:58:45 -07:00
parent d55ecd154b
commit de2bc18bbb
3 changed files with 10 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
vpr7_x2p/vpr/SRC/fpga_spice/spice/spice_lut.c
View File

@ -220,6 +220,9 @@ void fprint_pb_primitive_lut(FILE* fp,
/* Check if this is an idle logical block mapped*/
switch (lut_status) {
case PRIMITIVE_WIRED_LUT:
if (NULL == mapped_logical_block) {
break; /* Jump out if there is no mapped logical block */
}
/* Give a special truth table */
assert (VPACK_COMB == mapped_logical_block->type);
/* Get the mapped vpack_net_num of this physical LUT pb */

3
vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_lut.c
View File

@ -98,6 +98,9 @@ void dump_verilog_pb_primitive_lut(FILE* fp,
/* Check if this is an idle logical block mapped*/
switch (lut_status) {
case PRIMITIVE_WIRED_LUT:
if (NULL == mapped_logical_block) {
break; /* Jump out if there is no mapped logical block */
}
/* Give a special truth table */
assert (VPACK_COMB == mapped_logical_block->type);
/* Get the mapped vpack_net_num of this physical LUT pb */

6
vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_pbtypes.c
View File

@ -1993,12 +1993,14 @@ void dump_verilog_pb_graph_node_rec(FILE* fp,
pb_type_index, cur_pb_type->spice_model, PRIMITIVE_WIRED_LUT);
/* update the number of SRAM, I/O pads */
/* update stamped iopad counter */
stamped_iopad_cnt += cur_pb->num_iopads;
/* stamped_iopad_cnt += cur_pb->num_iopads; */
/* update stamped sram counter */
stamped_sram_cnt += cur_pb->num_conf_bits;
/* stamped_sram_cnt += cur_pb->num_conf_bits; */
/* Check */
/*
assert(stamped_sram_cnt == get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info));
assert(stamped_iopad_cnt == iopad_verilog_model->cnt);
*/
return;
}