From de2bc18bbb87e0f9e1e318666a784a0c97f1aa38 Mon Sep 17 00:00:00 2001 From: Aur??Lien ALACCHI Date: Mon, 26 Nov 2018 16:58:45 -0700 Subject: [PATCH] bugs fixed for shift register benchmark --- vpr7_x2p/vpr/SRC/fpga_spice/spice/spice_lut.c | 3 +++ vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_lut.c | 3 +++ vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_pbtypes.c | 6 ++++-- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_spice/spice/spice_lut.c b/vpr7_x2p/vpr/SRC/fpga_spice/spice/spice_lut.c index 21565cfa1..0573ecf8f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_spice/spice/spice_lut.c +++ b/vpr7_x2p/vpr/SRC/fpga_spice/spice/spice_lut.c @@ -220,6 +220,9 @@ void fprint_pb_primitive_lut(FILE* fp, /* Check if this is an idle logical block mapped*/ switch (lut_status) { case PRIMITIVE_WIRED_LUT: + if (NULL == mapped_logical_block) { + break; /* Jump out if there is no mapped logical block */ + } /* Give a special truth table */ assert (VPACK_COMB == mapped_logical_block->type); /* Get the mapped vpack_net_num of this physical LUT pb */ diff --git a/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_lut.c b/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_lut.c index 4b3ef3fa6..267d9732c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_lut.c +++ b/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_lut.c @@ -98,6 +98,9 @@ void dump_verilog_pb_primitive_lut(FILE* fp, /* Check if this is an idle logical block mapped*/ switch (lut_status) { case PRIMITIVE_WIRED_LUT: + if (NULL == mapped_logical_block) { + break; /* Jump out if there is no mapped logical block */ + } /* Give a special truth table */ assert (VPACK_COMB == mapped_logical_block->type); /* Get the mapped vpack_net_num of this physical LUT pb */ diff --git a/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_pbtypes.c index b388cb6e6..fc82cbdb3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_pbtypes.c @@ -1993,12 +1993,14 @@ void dump_verilog_pb_graph_node_rec(FILE* fp, pb_type_index, cur_pb_type->spice_model, PRIMITIVE_WIRED_LUT); /* update the number of SRAM, I/O pads */ /* update stamped iopad counter */ - stamped_iopad_cnt += cur_pb->num_iopads; + /* stamped_iopad_cnt += cur_pb->num_iopads; */ /* update stamped sram counter */ - stamped_sram_cnt += cur_pb->num_conf_bits; + /* stamped_sram_cnt += cur_pb->num_conf_bits; */ /* Check */ + /* assert(stamped_sram_cnt == get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info)); assert(stamped_iopad_cnt == iopad_verilog_model->cnt); + */ return; }