Mux explicit verilog done
This commit is contained in:
Baudouin Chauviere
parent
863e8677c0
commit
370ce23646
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@ -1153,7 +1153,8 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp,
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char* mux_basis_subckt_name,
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t_spice_model spice_model,
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t_spice_mux_arch spice_mux_arch,
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int num_sram_port, t_spice_model_port** sram_port) {
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int num_sram_port, t_spice_model_port** sram_port,
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bool is_explicit_mapping) {
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int i, j, level, nextlevel;
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int nextj, out_idx;
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int mux_basis_cnt = 0;
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@ -1225,17 +1226,41 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp,
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/* Each basis mux2to1: <given_name> <input0> <input1> <output> <sram> <sram_inv> svdd sgnd <subckt_name> */
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fprintf(fp, "%s mux_basis_no%d (", mux_basis_subckt_name, mux_basis_cnt); /* given_name */
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/* Dump global ports */
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if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) {
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if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
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fprintf(fp, ",\n");
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}
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if (true == is_explicit_mapping) {
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fprintf(fp, ".in(");
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}
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/* For intermediate buffers */
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if (TRUE == inter_buf_loc[level]) {
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fprintf(fp, "mux2_l%d_in_buf[%d:%d], ", level, j, nextj); /* input0 input1 */
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fprintf(fp, "mux2_l%d_in_buf[%d:%d]", level, j, nextj); /* input0 input1 */
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} else {
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fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, nextj); /* input0 input1 */
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fprintf(fp, "mux2_l%d_in[%d:%d]", level, j, nextj); /* input0 input1 */
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}
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if (true == is_explicit_mapping) {
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fprintf(fp, "), .out(");
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} else {
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fprintf(fp, ", ");
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}
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fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */
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if (true == is_explicit_mapping) {
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fprintf(fp, "), .mem(");
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} else {
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fprintf(fp, ", ");
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}
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fprintf(fp, "%s[%d]", sram_port[0]->prefix, i); /* sram */
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if (true == is_explicit_mapping) {
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fprintf(fp, "), .mem_inv(");
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} else {
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fprintf(fp, ", ");
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}
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fprintf(fp, "%s_inv[%d]", sram_port[0]->prefix, i); /* sram_inv */
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if (true == is_explicit_mapping) {
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fprintf(fp, "));\n");
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} else {
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fprintf(fp, ");\n");
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}
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fprintf(fp, "mux2_l%d_in[%d], ", nextlevel, out_idx); /* output */
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fprintf(fp, "%s[%d], %s_inv[%d]);\n", sram_port[0]->prefix, i, sram_port[0]->prefix, i); /* sram sram_inv */
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/* For intermediate buffers */
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if (TRUE == inter_buf_loc[nextlevel]) {
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/* Find the input port, output port, and sram port*/
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@ -1302,7 +1327,8 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp,
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char* mux_special_basis_subckt_name,
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t_spice_model spice_model,
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t_spice_mux_arch spice_mux_arch,
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int num_sram_port, t_spice_model_port** sram_port) {
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int num_sram_port, t_spice_model_port** sram_port,
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bool is_explicit_mapping) {
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int i, j, level, nextlevel, sram_idx;
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int out_idx;
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int mux_basis_cnt = 0;
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@ -1348,14 +1374,36 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp,
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/* Print the special basis */
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fprintf(fp, "%s special_basis(", mux_special_basis_subckt_name);
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/* Dump global ports */
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if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) {
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if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
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fprintf(fp, ",\n");
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}
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fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, j + cur_num_input_basis - 1); /* input0 input1 */
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fprintf(fp, "mux2_l%d_in[%d], ", nextlevel, out_idx); /* output */
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fprintf(fp, "%s[%d:%d], %s_inv[%d:%d] ",
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sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1,
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if (true == is_explicit_mapping) {
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fprintf(fp, ".in(");
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}
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fprintf(fp, "mux2_l%d_in[%d:%d]", level, j, j + cur_num_input_basis - 1); /* input0 input1 */
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if (true == is_explicit_mapping) {
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fprintf(fp, "), .out(");
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} else {
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fprintf(fp, ", ");
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}
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fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */
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if (true == is_explicit_mapping) {
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fprintf(fp, "), .mem(");
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} else {
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fprintf(fp, ", ");
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}
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fprintf(fp, "%s[%d:%d]",
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sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1);
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if (true == is_explicit_mapping) {
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fprintf(fp, "), .mem_inv(");
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} else {
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fprintf(fp, ", ");
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}
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fprintf(fp, "%s_inv[%d:%d]",
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sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1);
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if (true == is_explicit_mapping) {
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fprintf(fp, ")");
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}
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fprintf(fp, ");\n");
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special_basis_cnt++;
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}
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@ -1365,16 +1413,38 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp,
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fprintf(fp, "%s ", mux_basis_subckt_name); /* subckt_name */
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fprintf(fp, "mux_basis_no%d (", mux_basis_cnt); /* given_name */
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/* Dump global ports */
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if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) {
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if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
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fprintf(fp, ",\n");
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}
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fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, j + cur_num_input_basis - 1); /* input0 input1 */
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fprintf(fp, "mux2_l%d_in[%d], ", nextlevel, out_idx); /* output */
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if (true == is_explicit_mapping) {
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fprintf(fp, ".in(");
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}
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fprintf(fp, "mux2_l%d_in[%d:%d]", level, j, j + cur_num_input_basis - 1); /* input0 input1 */
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if (true == is_explicit_mapping) {
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fprintf(fp, "), .out(");
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} else {
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fprintf(fp, ", ");
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}
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fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */
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/* Print number of sram bits for this basis */
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fprintf(fp, "%s[%d:%d], %s_inv[%d:%d] ",
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sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1,
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if (true == is_explicit_mapping) {
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fprintf(fp, "), .mem(");
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} else {
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fprintf(fp, ", ");
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}
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fprintf(fp, "%s[%d:%d]",
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sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1);
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fprintf(fp, ");\n");
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if (true == is_explicit_mapping) {
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fprintf(fp, "), .mem_inv(");
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} else {
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fprintf(fp, ", ");
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}
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fprintf(fp, "%s_inv[%d:%d]",
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sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1);
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if (true == is_explicit_mapping) {
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fprintf(fp, ")");
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}
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fprintf(fp, ");");
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fprintf(fp, "\n");
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/* Update the counter */
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mux_basis_cnt++;
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@ -1393,7 +1463,8 @@ void dump_verilog_cmos_mux_onelevel_structure(FILE* fp,
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char* mux_basis_subckt_name,
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t_spice_model spice_model,
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t_spice_mux_arch spice_mux_arch,
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int num_sram_port, t_spice_model_port** sram_port) {
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int num_sram_port, t_spice_model_port** sram_port,
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bool is_explicit_mapping) {
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/* Make sure we have a valid file handler*/
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if (NULL == fp) {
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vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__);
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@ -1407,23 +1478,61 @@ void dump_verilog_cmos_mux_onelevel_structure(FILE* fp,
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fprintf(fp, "%s mux_basis (\n", mux_basis_subckt_name); /* given_name */
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/* Dump global ports */
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if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) {
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if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE,
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my_bool_to_boolean(is_explicit_mapping))) {
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fprintf(fp, ",\n");
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}
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fprintf(fp, "//----- MUX inputs -----\n");
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fprintf(fp, "mux2_l%d_in[0:%d], ", 1, spice_mux_arch.num_input - 1); /* input0 */
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fprintf(fp, "mux2_l%d_in[%d], ", 0, 0); /* output */
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if (true == is_explicit_mapping) {
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fprintf(fp, ".in(");
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}
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fprintf(fp, "mux2_l%d_in[0:%d]", 1, spice_mux_arch.num_input - 1); /* input0 */
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if (true == is_explicit_mapping) {
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fprintf(fp, "), .out(");
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} else {
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fprintf(fp, ", ");
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}
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fprintf(fp, "mux2_l%d_in[%d]", 0, 0); /* output */
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if (true == is_explicit_mapping) {
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fprintf(fp, "),");
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} else {
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fprintf(fp, ",");
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}
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fprintf(fp, "\n");
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fprintf(fp, "//----- SRAM ports -----\n");
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/* Special basis for 2-input MUX, there is only one configuration bit */
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if (2 == spice_mux_arch.num_input) {
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fprintf(fp, "%s[0:%d], %s_inv[0:%d] ",
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sram_port[0]->prefix, 0,
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sram_port[0]->prefix, 0); /* sram sram_inv */
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if (true == is_explicit_mapping) {
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fprintf(fp, ".mem(");
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}
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fprintf(fp, "%s[0:%d]",
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sram_port[0]->prefix, 0); /* sram */
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if (true == is_explicit_mapping) {
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fprintf(fp, "), .mem_inv(");
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} else {
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fprintf(fp, ", ");
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}
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fprintf(fp, "%s_inv[0:%d]",
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sram_port[0]->prefix, 0); /* sram_inv */
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if (true == is_explicit_mapping) {
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fprintf(fp, ")");
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}
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} else {
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fprintf(fp, "%s[0:%d], %s_inv[0:%d] ",
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sram_port[0]->prefix, spice_mux_arch.num_input - 1,
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sram_port[0]->prefix, spice_mux_arch.num_input - 1); /* sram sram_inv */
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if (true == is_explicit_mapping) {
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fprintf(fp, ".mem(");
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}
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fprintf(fp, "%s[0:%d]",
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sram_port[0]->prefix, spice_mux_arch.num_input - 1); /* sram */
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if (true == is_explicit_mapping) {
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fprintf(fp, "), .mem_inv(");
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} else {
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fprintf(fp, ", ");
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}
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fprintf(fp, "%s_inv[0:%d]",
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sram_port[0]->prefix, spice_mux_arch.num_input - 1); /* sram_inv */
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if (true == is_explicit_mapping) {
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fprintf(fp, ")");
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}
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}
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fprintf(fp, "\n");
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fprintf(fp, ");\n");
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@ -1542,7 +1651,7 @@ void dump_verilog_cmos_mux_submodule(FILE* fp,
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} else {
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fprintf(fp, "//----- CMOS MUX info: spice_model_name=%s, size=%d, structure: %s -----\n",
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spice_model.name, mux_size, gen_str_spice_model_structure(spice_model.design_tech_info.mux_info->structure));
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fprintf(fp, "module %s (",
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fprintf(fp, "module %s (\n",
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gen_verilog_one_mux_module_name(&spice_model, mux_size));
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/* Print input ports*/
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fprintf(fp, "input wire [0:%d] %s,\n", mux_size - 1, input_port[0]->prefix);
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@ -1569,15 +1678,17 @@ void dump_verilog_cmos_mux_submodule(FILE* fp,
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switch (cur_mux_structure) {
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case SPICE_MODEL_STRUCTURE_TREE:
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dump_verilog_cmos_mux_tree_structure(fp, mux_basis_subckt_name,
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spice_model, spice_mux_arch, num_sram_port, sram_port);
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spice_model, spice_mux_arch, num_sram_port, sram_port, is_explicit_mapping);
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break;
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case SPICE_MODEL_STRUCTURE_ONELEVEL:
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dump_verilog_cmos_mux_onelevel_structure(fp, mux_basis_subckt_name,
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spice_model, spice_mux_arch, num_sram_port, sram_port);
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spice_model, spice_mux_arch,
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num_sram_port, sram_port, is_explicit_mapping);
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break;
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case SPICE_MODEL_STRUCTURE_MULTILEVEL:
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dump_verilog_cmos_mux_multilevel_structure(fp, mux_basis_subckt_name, mux_special_basis_subckt_name,
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spice_model, spice_mux_arch, num_sram_port, sram_port);
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spice_model, spice_mux_arch, num_sram_port, sram_port,
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is_explicit_mapping);
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break;
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default:
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vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice model (%s)!\n",
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