From 370ce23646e00197b79b572600e6fc9e5940c453 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Mon, 1 Jul 2019 13:58:24 -0600 Subject: [PATCH] Mux explicit verilog done --- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 175 ++++++++++++++---- 1 file changed, 143 insertions(+), 32 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 5bcc70cb8..6b985dc70 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -1153,7 +1153,8 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, char* mux_basis_subckt_name, t_spice_model spice_model, t_spice_mux_arch spice_mux_arch, - int num_sram_port, t_spice_model_port** sram_port) { + int num_sram_port, t_spice_model_port** sram_port, + bool is_explicit_mapping) { int i, j, level, nextlevel; int nextj, out_idx; int mux_basis_cnt = 0; @@ -1225,17 +1226,41 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, /* Each basis mux2to1: svdd sgnd */ fprintf(fp, "%s mux_basis_no%d (", mux_basis_subckt_name, mux_basis_cnt); /* given_name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } + if (true == is_explicit_mapping) { + fprintf(fp, ".in("); + } /* For intermediate buffers */ if (TRUE == inter_buf_loc[level]) { - fprintf(fp, "mux2_l%d_in_buf[%d:%d], ", level, j, nextj); /* input0 input1 */ + fprintf(fp, "mux2_l%d_in_buf[%d:%d]", level, j, nextj); /* input0 input1 */ } else { - fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, nextj); /* input0 input1 */ + fprintf(fp, "mux2_l%d_in[%d:%d]", level, j, nextj); /* input0 input1 */ + } + if (true == is_explicit_mapping) { + fprintf(fp, "), .out("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s[%d]", sram_port[0]->prefix, i); /* sram */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem_inv("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s_inv[%d]", sram_port[0]->prefix, i); /* sram_inv */ + if (true == is_explicit_mapping) { + fprintf(fp, "));\n"); + } else { + fprintf(fp, ");\n"); } - fprintf(fp, "mux2_l%d_in[%d], ", nextlevel, out_idx); /* output */ - fprintf(fp, "%s[%d], %s_inv[%d]);\n", sram_port[0]->prefix, i, sram_port[0]->prefix, i); /* sram sram_inv */ /* For intermediate buffers */ if (TRUE == inter_buf_loc[nextlevel]) { /* Find the input port, output port, and sram port*/ @@ -1302,7 +1327,8 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, char* mux_special_basis_subckt_name, t_spice_model spice_model, t_spice_mux_arch spice_mux_arch, - int num_sram_port, t_spice_model_port** sram_port) { + int num_sram_port, t_spice_model_port** sram_port, + bool is_explicit_mapping) { int i, j, level, nextlevel, sram_idx; int out_idx; int mux_basis_cnt = 0; @@ -1348,14 +1374,36 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, /* Print the special basis */ fprintf(fp, "%s special_basis(", mux_special_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } - fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, j + cur_num_input_basis - 1); /* input0 input1 */ - fprintf(fp, "mux2_l%d_in[%d], ", nextlevel, out_idx); /* output */ - fprintf(fp, "%s[%d:%d], %s_inv[%d:%d] ", - sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1, + if (true == is_explicit_mapping) { + fprintf(fp, ".in("); + } + fprintf(fp, "mux2_l%d_in[%d:%d]", level, j, j + cur_num_input_basis - 1); /* input0 input1 */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .out("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s[%d:%d]", sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1); + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem_inv("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s_inv[%d:%d]", + sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ");\n"); special_basis_cnt++; } @@ -1365,16 +1413,38 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, fprintf(fp, "%s ", mux_basis_subckt_name); /* subckt_name */ fprintf(fp, "mux_basis_no%d (", mux_basis_cnt); /* given_name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } - fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, j + cur_num_input_basis - 1); /* input0 input1 */ - fprintf(fp, "mux2_l%d_in[%d], ", nextlevel, out_idx); /* output */ + if (true == is_explicit_mapping) { + fprintf(fp, ".in("); + } + fprintf(fp, "mux2_l%d_in[%d:%d]", level, j, j + cur_num_input_basis - 1); /* input0 input1 */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .out("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */ /* Print number of sram bits for this basis */ - fprintf(fp, "%s[%d:%d], %s_inv[%d:%d] ", - sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1, + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s[%d:%d]", sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1); - fprintf(fp, ");\n"); + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem_inv("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s_inv[%d:%d]", + sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } + fprintf(fp, ");"); fprintf(fp, "\n"); /* Update the counter */ mux_basis_cnt++; @@ -1393,7 +1463,8 @@ void dump_verilog_cmos_mux_onelevel_structure(FILE* fp, char* mux_basis_subckt_name, t_spice_model spice_model, t_spice_mux_arch spice_mux_arch, - int num_sram_port, t_spice_model_port** sram_port) { + int num_sram_port, t_spice_model_port** sram_port, + bool is_explicit_mapping) { /* Make sure we have a valid file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); @@ -1407,23 +1478,61 @@ void dump_verilog_cmos_mux_onelevel_structure(FILE* fp, fprintf(fp, "%s mux_basis (\n", mux_basis_subckt_name); /* given_name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, + my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } fprintf(fp, "//----- MUX inputs -----\n"); - fprintf(fp, "mux2_l%d_in[0:%d], ", 1, spice_mux_arch.num_input - 1); /* input0 */ - fprintf(fp, "mux2_l%d_in[%d], ", 0, 0); /* output */ + if (true == is_explicit_mapping) { + fprintf(fp, ".in("); + } + fprintf(fp, "mux2_l%d_in[0:%d]", 1, spice_mux_arch.num_input - 1); /* input0 */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .out("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "mux2_l%d_in[%d]", 0, 0); /* output */ + if (true == is_explicit_mapping) { + fprintf(fp, "),"); + } else { + fprintf(fp, ","); + } fprintf(fp, "\n"); fprintf(fp, "//----- SRAM ports -----\n"); /* Special basis for 2-input MUX, there is only one configuration bit */ if (2 == spice_mux_arch.num_input) { - fprintf(fp, "%s[0:%d], %s_inv[0:%d] ", - sram_port[0]->prefix, 0, - sram_port[0]->prefix, 0); /* sram sram_inv */ + if (true == is_explicit_mapping) { + fprintf(fp, ".mem("); + } + fprintf(fp, "%s[0:%d]", + sram_port[0]->prefix, 0); /* sram */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem_inv("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s_inv[0:%d]", + sram_port[0]->prefix, 0); /* sram_inv */ + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } } else { - fprintf(fp, "%s[0:%d], %s_inv[0:%d] ", - sram_port[0]->prefix, spice_mux_arch.num_input - 1, - sram_port[0]->prefix, spice_mux_arch.num_input - 1); /* sram sram_inv */ + if (true == is_explicit_mapping) { + fprintf(fp, ".mem("); + } + fprintf(fp, "%s[0:%d]", + sram_port[0]->prefix, spice_mux_arch.num_input - 1); /* sram */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem_inv("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s_inv[0:%d]", + sram_port[0]->prefix, spice_mux_arch.num_input - 1); /* sram_inv */ + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } } fprintf(fp, "\n"); fprintf(fp, ");\n"); @@ -1542,7 +1651,7 @@ void dump_verilog_cmos_mux_submodule(FILE* fp, } else { fprintf(fp, "//----- CMOS MUX info: spice_model_name=%s, size=%d, structure: %s -----\n", spice_model.name, mux_size, gen_str_spice_model_structure(spice_model.design_tech_info.mux_info->structure)); - fprintf(fp, "module %s (", + fprintf(fp, "module %s (\n", gen_verilog_one_mux_module_name(&spice_model, mux_size)); /* Print input ports*/ fprintf(fp, "input wire [0:%d] %s,\n", mux_size - 1, input_port[0]->prefix); @@ -1569,15 +1678,17 @@ void dump_verilog_cmos_mux_submodule(FILE* fp, switch (cur_mux_structure) { case SPICE_MODEL_STRUCTURE_TREE: dump_verilog_cmos_mux_tree_structure(fp, mux_basis_subckt_name, - spice_model, spice_mux_arch, num_sram_port, sram_port); + spice_model, spice_mux_arch, num_sram_port, sram_port, is_explicit_mapping); break; case SPICE_MODEL_STRUCTURE_ONELEVEL: dump_verilog_cmos_mux_onelevel_structure(fp, mux_basis_subckt_name, - spice_model, spice_mux_arch, num_sram_port, sram_port); + spice_model, spice_mux_arch, + num_sram_port, sram_port, is_explicit_mapping); break; case SPICE_MODEL_STRUCTURE_MULTILEVEL: dump_verilog_cmos_mux_multilevel_structure(fp, mux_basis_subckt_name, mux_special_basis_subckt_name, - spice_model, spice_mux_arch, num_sram_port, sram_port); + spice_model, spice_mux_arch, num_sram_port, sram_port, + is_explicit_mapping); break; default: vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice model (%s)!\n",