Bug Fix

2019-06-26 08:53:46 -06:00 · 2019-06-26 08:53:46 -06:00 · 56557b94e7
parent bb250ddef9
commit 56557b94e7
1 changed files with 0 additions and 1 deletions
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c
@ -999,7 +999,6 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
          break;
        case CHANX:
        case CHANY:
-verilog_generate_report_timing_one_sb_ending_segments
          /* Get the coordinate of ending SB */
          next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
          next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);