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Top module done

This commit is contained in:
Baudouin Chauviere 2019-07-08 09:48:33 -06:00
parent b08513d902
commit ae05c553d5
9 changed files with 131 additions and 34 deletions
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14
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
View File

@ -361,7 +361,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
fprintf(fp, "module %s ( \n", subckt_name);
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) {
fprintf(fp, ",\n");
}
@ -378,7 +378,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
/* I/O PAD */
dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix,
0, phy_block_type->capacity * phy_block_type->pb_type->physical_mode_num_iopads - 1,
VERILOG_PORT_INOUT);
VERILOG_PORT_INOUT, is_explicit_mapping);
/* Print configuration ports */
/* Reserved configuration ports */
@ -406,7 +406,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
0,
temp_conf_bits_msb - 1,
VERILOG_PORT_INPUT, is_explicit_mapping); // Should be modified to be VERILOG_PORT_INPUT
VERILOG_PORT_INPUT, false); // Should be modified to be VERILOG_PORT_INPUT
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -436,9 +436,9 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
/* Print all the pins */
/* Special Care for I/O grid */
if (IO_TYPE == phy_block_type) {
dump_compact_verilog_io_grid_block_subckt_pins(fp, phy_block_type, border_side, iz);
dump_compact_verilog_io_grid_block_subckt_pins(fp, phy_block_type, border_side, iz, is_explicit_mapping);
} else {
dump_verilog_grid_block_subckt_pins(fp, iz, phy_block_type);
dump_verilog_grid_block_subckt_pins(fp, iz, phy_block_type, is_explicit_mapping);
}
/* Print configuration ports */
@ -450,7 +450,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
fprintf(fp, "\n//---- IOPAD ----\n");
dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix,
temp_iopad_lsb, temp_iopad_msb - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
/* Reserved configuration ports */
if (0 < temp_reserved_conf_bits_msb) {
fprintf(fp, ",\n");
@ -631,7 +631,7 @@ void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix,
iopad_verilog_model->grid_index_low[ix][iy],
iopad_verilog_model->grid_index_high[ix][iy] - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
/* Print configuration ports */
/* Reserved configuration ports */

52
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
View File

@ -370,8 +370,7 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp,
port_prefix, pb_type_port->name);
} else {
if ((NULL != cur_pb_type->spice_model)
&& (TRUE == dump_explicit_port_map)
&& (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) {
&& (TRUE == dump_explicit_port_map)) {
fprintf(fp, ".%s(",
pb_type_port->spice_model_port->lib_name);
}
@ -385,8 +384,7 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp,
}
fprintf(fp, "}");
if ((NULL != cur_pb_type->spice_model)
&& (TRUE == dump_explicit_port_map)
&& (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) {
&& (TRUE == dump_explicit_port_map)) {
fprintf(fp, ")");
}
}
@ -1733,7 +1731,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
*/
fprintf(fp, "\n");
/* dump global ports */
if(0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) {
if(0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) {
fprintf(fp, ",\n");
}
/* Simplify the port prefix, make SPICE netlist readable */
@ -1742,7 +1740,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_grid_common_port(fp, iopad_verilog_model,
gio_inout_prefix,
stamped_iopad_cnt, iopad_verilog_model->cnt - 1,
VERILOG_PORT_INOUT);
VERILOG_PORT_INOUT, is_explicit_mapping);
/* Print Configuration ports */
/* sram_verilog_model->cnt should be updated because all the child pbs have been dumped
* stamped_sram_cnt remains the old sram_verilog_model->cnt before all the child pbs are dumped
@ -1848,7 +1846,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
gio_inout_prefix,
stamped_iopad_cnt,
stamped_iopad_cnt + child_pb_num_iopads - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
/* update stamped outpad counter */
stamped_iopad_cnt += child_pb_num_iopads;
/* Print configuration ports */
@ -1889,7 +1887,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
/* Print interconnections, set is_idle as TRUE*/
dump_verilog_pb_graph_interc(cur_sram_orgz_info, fp, subckt_name,
cur_pb_graph_node, mode_index,
is_explicit_mapping);
false);
/* Check each pins of pb_graph_node */
/* Check and update stamped_sram_cnt */
/* Now we only dump one Verilog for each pb_type, and instance them when num_pb > 1
@ -2279,9 +2277,11 @@ char* verilog_get_grid_phy_block_subckt_name(int x, int y, int z,
/* Print the pins of grid subblocks */
void dump_verilog_grid_block_subckt_pins(FILE* fp,
int z,
t_type_ptr type_descriptor) {
t_type_ptr type_descriptor,
bool is_explicit_mapping) {
int iport, ipin, side, dump_pin_cnt;
int grid_pin_index, pin_height, side_pin_index;
t_port* cur_port;
t_pb_graph_node* top_pb_graph_node = NULL;
/* Check the file handler*/
@ -2313,8 +2313,15 @@ void dump_verilog_grid_block_subckt_pins(FILE* fp,
if (0 < dump_pin_cnt) {
fprintf(fp, ",\n");
}
if (true == is_explicit_mapping) {
fprintf(fp, ".%s (",
gen_verilog_one_pb_type_pin_name(chomp_verilog_prefix(top_pb_graph_node->pb_type->name), top_pb_graph_node->input_pins[iport]->port, ipin));
}
fprintf(fp, "%s_height_%d__pin_%d_ ",
convert_side_index_to_string(side), pin_height, grid_pin_index);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
dump_pin_cnt++;
side_pin_index++;
}
@ -2338,8 +2345,15 @@ void dump_verilog_grid_block_subckt_pins(FILE* fp,
if (0 < dump_pin_cnt) {
fprintf(fp, ",\n");
}
if (true == is_explicit_mapping) {
fprintf(fp, ".%s (",
gen_verilog_one_pb_type_pin_name(chomp_verilog_prefix(top_pb_graph_node->pb_type->name), top_pb_graph_node->output_pins[iport]->port, ipin));
}
fprintf(fp, "%s_height_%d__pin_%d_ ",
convert_side_index_to_string(side), pin_height, grid_pin_index);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
dump_pin_cnt++;
side_pin_index++;
}
@ -2363,8 +2377,15 @@ void dump_verilog_grid_block_subckt_pins(FILE* fp,
if (0 < dump_pin_cnt) {
fprintf(fp, ",\n");
}
if (true == is_explicit_mapping) {
fprintf(fp, ".%s (",
gen_verilog_one_pb_type_pin_name(chomp_verilog_prefix(top_pb_graph_node->pb_type->name), top_pb_graph_node->clock_pins[iport]->port, ipin));
}
fprintf(fp, "%s_height_%d__pin_%d_ ",
convert_side_index_to_string(side), pin_height, grid_pin_index);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
dump_pin_cnt++;
side_pin_index++;
}
@ -2381,7 +2402,8 @@ void dump_verilog_io_grid_block_subckt_pins(FILE* fp,
int x,
int y,
int z,
t_type_ptr type_descriptor) {
t_type_ptr type_descriptor,
bool is_explicit_mapping) {
int iport, ipin, side, dump_pin_cnt;
int grid_pin_index, pin_height, side_pin_index;
t_pb_graph_node* top_pb_graph_node = NULL;
@ -2552,7 +2574,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "module %s ( \n", gen_verilog_one_grid_module_name(ix, iy));
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) {
fprintf(fp, ",\n");
}
@ -2568,7 +2590,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix,
iopad_verilog_model->grid_index_low[ix][iy],
iopad_verilog_model->grid_index_high[ix][iy] - 1,
VERILOG_PORT_INPUT);
VERILOG_PORT_INPUT, is_explicit_mapping);
/* Print configuration ports */
/* Reserved configuration ports */
@ -2631,9 +2653,9 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info,
/* Print all the pins */
/* Special Care for I/O grid */
if (IO_TYPE == grid[ix][iy].type) {
dump_verilog_io_grid_block_subckt_pins(fp, ix, iy, iz, grid[ix][iy].type);
dump_verilog_io_grid_block_subckt_pins(fp, ix, iy, iz, grid[ix][iy].type, is_explicit_mapping);
} else {
dump_verilog_grid_block_subckt_pins(fp, iz, grid[ix][iy].type);
dump_verilog_grid_block_subckt_pins(fp, iz, grid[ix][iy].type, is_explicit_mapping);
}
/* Print configuration ports */
temp_reserved_conf_bits_msb = grid[ix][iy].type->pb_type->physical_mode_num_reserved_conf_bits;
@ -2645,7 +2667,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix,
temp_iopad_lsb,
temp_iopad_msb - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
assert(!(0 > temp_conf_bits_msb - temp_conf_bits_lsb));
/* Reserved configuration ports */
if (0 < temp_reserved_conf_bits_msb) {

3
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h
View File

@ -127,7 +127,8 @@ char* get_grid_block_subckt_name(int x,
void dump_verilog_grid_block_subckt_pins(FILE* fp,
int z,
t_type_ptr type_descriptor);
t_type_ptr type_descriptor,
bool is_explicit_mapping);
void dump_verilog_io_grid_block_subckt_pins(FILE* fp,
int x,

54
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c
View File

@ -610,7 +610,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
/* Connect inputs*/
/* Connect outputs*/
fprintf(fp, "//----- Input and output ports -----\n");
dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, cur_pb_type, FALSE, TRUE, verilog_model->dump_explicit_port_map);
dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, cur_pb_type, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping));
fprintf(fp, "\n//----- SRAM ports -----\n");
/* check */
@ -622,41 +622,89 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
case SPICE_SRAM_STANDALONE:
break;
case SPICE_SRAM_SCAN_CHAIN:
if (true == is_explicit_mapping) {
fprintf(fp, ".sram_out( ");
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_lut_sram - 1,
0, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
if (true == is_explicit_mapping) {
fprintf(fp, ".sram_outb( ");
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_lut_sram - 1,
1, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
if (0 < num_mode_sram) {
fprintf(fp, ", ");
if (true == is_explicit_mapping) {
fprintf(fp, ".mode_out( ");
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1,
0, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
if (true == is_explicit_mapping) {
fprintf(fp, ".mode_outb( ");
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1,
1, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
}
break;
case SPICE_SRAM_MEMORY_BANK:
if (true == is_explicit_mapping) {
fprintf(fp, ".sram_out( ");
}
dump_verilog_sram_one_outport(fp, cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_lut_sram - 1,
0, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
if (true == is_explicit_mapping) {
fprintf(fp, ".sram_outb( ");
}
dump_verilog_sram_one_outport(fp, cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_lut_sram - 1,
1, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
if (0 < num_mode_sram) {
fprintf(fp, ", ");
if (true == is_explicit_mapping) {
fprintf(fp, ".mode_out( ");
}
dump_verilog_sram_one_outport(fp, cur_sram_orgz_info,
cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1,
0, VERILOG_PORT_CONKT);
0, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
if (true == is_explicit_mapping) {
fprintf(fp, ".mode_outb( ");
}
dump_verilog_sram_one_outport(fp, cur_sram_orgz_info,
cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1,
1, VERILOG_PORT_CONKT);
1, VERILOG_PORT_CONKT);
}
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
break;
default:

4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
View File

@ -1900,7 +1900,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr
dump_verilog_routing_switch_box_unique_side_subckt_portmap(fp, rr_sb, side,
seg_id, TRUE,
is_explicit_mapping);
false);
/* Put down configuration port */
/* output of each configuration bit */
@ -1926,7 +1926,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_num_sram,
esti_sram_cnt - 1,
VERILOG_PORT_INPUT, is_explicit_mapping);
VERILOG_PORT_INPUT, false);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}

5
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c
View File

@ -405,7 +405,7 @@ void dump_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix,
iopad_verilog_model->grid_index_low[ix][iy],
iopad_verilog_model->grid_index_high[ix][iy] - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
/* Print configuration ports */
/* Reserved configuration ports */
@ -1433,7 +1433,8 @@ char* compact_verilog_get_grid_phy_block_subckt_name(t_type_ptr grid_type_descri
void dump_compact_verilog_io_grid_block_subckt_pins(FILE* fp,
t_type_ptr grid_type_descriptor,
int border_side,
int z) {
int z,
bool is_explicit_mapping) {
int iport, ipin, dump_pin_cnt;
int grid_pin_index, pin_height, side_pin_index;
t_pb_graph_node* top_pb_graph_node = NULL;

3
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h
View File

@ -52,6 +52,7 @@ char* compact_verilog_get_grid_phy_block_subckt_name(t_type_ptr grid_type_descri
void dump_compact_verilog_io_grid_block_subckt_pins(FILE* fp,
t_type_ptr grid_type_descriptor,
int border_side,
int z) ;
int z,
bool is_explicit_mapping) ;

24
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c
View File

@ -2717,7 +2717,8 @@ void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model,
*/
void dump_verilog_grid_common_port(FILE* fp, t_spice_model* cur_verilog_model,
char* general_port_prefix, int lsb, int msb,
enum e_dump_verilog_port_type dump_port_type) {
enum e_dump_verilog_port_type dump_port_type,
bool is_explicit_mapping) {
char* port_full_name = NULL;
/* Check the file handler*/
@ -3238,18 +3239,39 @@ void dump_verilog_mem_sram_submodule(FILE* fp,
break;
}
/* Input of Scan-chain DFF, should be connected to the output of its precedent */
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
cur_sram_verilog_model->ports[0].prefix);
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
lsb, msb,
-1, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", \n"); //
/* Output of Scan-chain DFF, should be connected to the output of its successor */
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
cur_sram_verilog_model->ports[1].prefix);
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
lsb, msb,
0, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", \n"); //
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
cur_sram_verilog_model->ports[2].prefix);
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
lsb, msb,
1, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
break;
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid SRAM organization type!\n",

6
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h
View File

@ -100,7 +100,8 @@ void dump_verilog_mux_sram_one_local_outport(FILE* fp,
t_spice_model* cur_mux_spice_model, int mux_size,
int sram_lsb, int sram_msb,
int port_type_index,
enum e_dump_verilog_port_type dump_port_type);
enum e_dump_verilog_port_type dump_port_type,
bool is_explicit_mapping);
void dump_verilog_sram_one_local_outport(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
@ -202,7 +203,8 @@ void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model,
void dump_verilog_grid_common_port(FILE* fp, t_spice_model* cur_verilog_model,
char* general_port_prefix, int lsb, int msb,
enum e_dump_verilog_port_type dump_port_type);
enum e_dump_verilog_port_type dump_port_type,
bool is_explicit_mapping);
void dump_verilog_sram_config_bus_internal_wires(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info,
int lsb, int msb);