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fpga_flow bug fix + upload k8 architecture

This commit is contained in:
AurelienUoU 2019-07-16 07:04:45 -06:00
parent 35e1962732
commit b810b5cab9
4 changed files with 1144 additions and 5 deletions
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1139
fpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml Normal file
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File diff suppressed because it is too large Load Diff

6
fpga_flow/scripts/fpga_flow.pl
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@ -1358,9 +1358,6 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $)
if ("on" eq $opt_ptr->{vpr_fpga_x2p_sim_window_size}) {
$vpr_spice_opts = $vpr_spice_opts." --fpga_x2p_sim_window_size $opt_ptr->{vpr_fpga_x2p_sim_window_size_val}";
}
if ("on" eq $opt_ptr->{vpr_fpga_x2p_compact_routing_hierarchy}) {
$vpr_spice_opts = $vpr_spice_opts." --fpga_x2p_compact_routing_hierarchy";
}
if ("on" eq $opt_ptr->{vpr_fpga_spice_sim_mt_num}) {
$vpr_spice_opts = $vpr_spice_opts." --fpga_spice_sim_mt_num $opt_ptr->{vpr_fpga_spice_sim_mt_num_val}";
}
@ -1446,6 +1443,9 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $)
if ("on" eq $opt_ptr->{vpr_fpga_verilog_explicit_mapping}) {
$vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_explicit_mapping";
}
if ("on" eq $opt_ptr->{vpr_fpga_x2p_compact_routing_hierarchy}) {
$vpr_spice_opts = $vpr_spice_opts." --fpga_x2p_compact_routing_hierarchy";
}
}
# FPGA Bitstream Generator Options

2
fpga_flow/tuto_fpga_flow.sh
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@ -28,6 +28,6 @@ perl rewrite_path_in_file.pl -i $ff_path -k $dir_keyword $verilog_path # Set the
# SRAM FPGA
# TT case
perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power -vpr_fpga_verilog_print_user_defined_template -vpr_fpga_verilog_print_report_timing_tcl -vpr_fpga_verilog_print_sdc_pnr -vpr_fpga_verilog_print_sdc_analysis -vpr_fpga_x2p_compact_routing_hierarchy -end_flow_with_test -vpr_fpga_verilog_explicit_mapping -vpr_fpga_x2p_compact_routing_hierarchy
perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power -vpr_fpga_verilog_print_user_defined_template -vpr_fpga_verilog_print_report_timing_tcl -vpr_fpga_verilog_print_sdc_pnr -vpr_fpga_verilog_print_sdc_analysis -vpr_fpga_x2p_compact_routing_hierarchy -end_flow_with_test -vpr_fpga_verilog_explicit_mapping
echo "Netlists successfully generated and tested"

2
vpr7_x2p/vpr/regression_verilog.sh
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@ -14,7 +14,7 @@ arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xm
blif_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.blif"
act_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.act "
verilog_reference="${OpenFPGA_path}/fpga_flow/benchmarks/Verilog/Test_Modes/$benchmark.v"
vpr_route_chan_width="200"
vpr_route_chan_width="300"
fpga_flow_script="${OpenFPGA_path}/fpga_flow/scripts"
ff_path="$vpr_path/VerilogNetlists/ff.v"
new_ff_path="$verilog_output_dirpath/$verilog_output_dirname/SRC/ff.v"