start developing tileable_rr_graph_builder
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@ -150,9 +150,6 @@ static void build_rr_ychan(INP int i, INP int j,
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INP boolean * L_rr_edge_done, INOUTP t_rr_node * L_rr_node,
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INP int wire_to_ipin_switch, INP enum e_directionality directionality);
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static void rr_graph_externals(t_timing_inf timing_inf,
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t_segment_inf * segment_inf, int num_seg_types, int nodes_per_chan,
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int wire_to_ipin_switch, enum e_base_cost_type base_cost_type);
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void alloc_and_load_edges_and_switches(INP t_rr_node * L_rr_node, INP int inode,
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INP int num_edges, INP boolean * L_rr_edge_done,
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@ -202,10 +199,6 @@ static t_seg_details *alloc_and_load_global_route_seg_details(
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/* UDSD Modifications by WMF End */
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static int **alloc_and_load_actual_fc(INP int L_num_types, INP t_type_ptr types,
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INP int nodes_per_chan, INP boolean is_Fc_out,
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INP enum e_directionality directionality, OUTP boolean * Fc_clipped, INP boolean ignore_Fc_0);
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/******************* Subroutine definitions *******************************/
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void build_rr_graph(INP t_graph_type graph_type, INP int L_num_types,
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@ -295,8 +288,7 @@ void build_rr_graph(INP t_graph_type graph_type, INP int L_num_types,
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if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_SEG_DETAILS)) {
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dump_seg_details(seg_details, nodes_per_chan,
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getEchoFileName(E_ECHO_SEG_DETAILS));
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} else
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;
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}
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}
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/* END SEG_DETAILS */
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@ -539,7 +531,7 @@ void build_rr_graph(INP t_graph_type graph_type, INP int L_num_types,
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}
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}
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static void rr_graph_externals(t_timing_inf timing_inf,
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void rr_graph_externals(t_timing_inf timing_inf,
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t_segment_inf * segment_inf, int num_seg_types, int nodes_per_chan,
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int wire_to_ipin_switch, enum e_base_cost_type base_cost_type) {
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add_rr_graph_C_from_switches(timing_inf.C_ipin_cblock);
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@ -619,7 +611,7 @@ alloc_and_load_global_route_seg_details(INP int nodes_per_chan,
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}
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/* Calculates the actual Fc values for the given nodes_per_chan value */
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static int **
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int **
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alloc_and_load_actual_fc(INP int L_num_types, INP t_type_ptr types,
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INP int nodes_per_chan, INP boolean is_Fc_out,
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INP enum e_directionality directionality, OUTP boolean * Fc_clipped, INP boolean ignore_Fc_0) {
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@ -54,5 +54,14 @@ void load_net_rr_terminals(t_ivec *** L_rr_node_indices);
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void print_rr_node(FILE *fp, t_rr_node *L_rr_node, int inode);
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int **
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alloc_and_load_actual_fc(INP int L_num_types, INP t_type_ptr types,
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INP int nodes_per_chan, INP boolean is_Fc_out,
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INP enum e_directionality directionality, OUTP boolean * Fc_clipped, INP boolean ignore_Fc_0);
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void rr_graph_externals(t_timing_inf timing_inf,
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t_segment_inf * segment_inf, int num_seg_types, int nodes_per_chan,
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int wire_to_ipin_switch, enum e_base_cost_type base_cost_type);
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#endif
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@ -307,7 +307,7 @@ alloc_and_load_seg_details(INOUTP int *nodes_per_chan, INP int max_len,
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length * sizeof(boolean));
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seg_details[cur_track].sb = (boolean *) my_malloc(
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(length + 1) * sizeof(boolean));
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for (j = 0; j < length; ++j) {
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for (j = 0; j < length; ++j) { /* apply connection block existence */
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if (is_global_graph) {
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seg_details[cur_track].cb[j] = TRUE;
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} else {
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@ -328,7 +328,7 @@ alloc_and_load_seg_details(INOUTP int *nodes_per_chan, INP int max_len,
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seg_details[cur_track].cb[j] = segment_inf[i].cb[index];
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}
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}
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for (j = 0; j < (length + 1); ++j) {
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for (j = 0; j < (length + 1); ++j) { /* apply switch block existence */
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if (is_global_graph) {
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seg_details[cur_track].sb[j] = TRUE;
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} else {
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