Merge branch 'multimode_clb' into tileable_routing
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b359893852
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@ -13,7 +13,6 @@ cd fpga_flow/scripts
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perl rewrite_path_in_file.pl -i ../arch/template/k6_N10_sram_chain_HC_template.xml
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perl rewrite_path_in_file.pl -i ../../vpr7_x2p/vpr/regression_verilog.sh
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perl rewrite_path_in_file.pl -i ../../vpr7_x2p/vpr/
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perl rewrite_path_in_file.pl -i ../../vpr7_x2p/vpr/VerilogNetlists/ff.v
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cd -
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