Add new benchmark and modify go.sh to use it
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AurelienUoU
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@ -0,0 +1,40 @@
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clk 0.511800 0.202800
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rst 0.00001 0.198000
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a0 0.465000 0.196200
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a1 0.476000 0.196200
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a2 0.480800 0.203200
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a3 0.523200 0.203400
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b0 0.502800 0.211200
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b1 0.479200 0.208400
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b2 0.495200 0.197000
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b3 0.521000 0.204800
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cin 0.490400 0.194600
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reg_b[3] 0.250800 0.189200
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reg_cin 0.241600 0.168200
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cout 0.197600 0.171000
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sumout0 0.197400 0.197200
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sumout1 0.195200 0.205800
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sumout2 0.202000 0.213000
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sumout3 0.191600 0.207600
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reg_a[0] 0.229800 0.171000
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reg_a[1] 0.236000 0.170200
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reg_a[2] 0.230000 0.174400
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reg_a[3] 0.258400 0.179800
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reg_b[0] 0.250600 0.180400
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reg_b[1] 0.238600 0.177800
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reg_b[2] 0.248000 0.177400
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n83 0.250600 0.044471
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n88 0.238600 0.047498
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n93 0.248000 0.044135
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n33 0.250800 0.041399
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n38 0.241600 0.044556
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n43 0.197600 0.011311
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n67 0.767600 0.013393
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n47 0.197400 0.040388
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n51 0.195200 0.019975
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n55 0.202000 0.042318
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n59 0.191600 0.007901
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n63 0.229800 0.048269
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n68 0.236000 0.046714
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n73 0.230000 0.046748
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n78 0.258400 0.040977
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@ -0,0 +1,91 @@
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# Benchmark "sync_4bits_add" written by ABC on Sat Dec 22 05:55:54 2018
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.model sync_4bits_add
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.inputs clk rst a0 a1 a2 a3 b0 b1 b2 b3 cin
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.outputs sumout0 sumout1 sumout2 sumout3 cout
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.latch n33 reg_b[3] re clk 0
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.latch n38 reg_cin re clk 0
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.latch n43 cout re clk 0
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.latch n47 sumout0 re clk 0
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.latch n51 sumout1 re clk 0
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.latch n55 sumout2 re clk 0
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.latch n59 sumout3 re clk 0
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.latch n63 reg_a[0] re clk 0
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.latch n68 reg_a[1] re clk 0
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.latch n73 reg_a[2] re clk 0
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.latch n78 reg_a[3] re clk 0
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.latch n83 reg_b[0] re clk 0
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.latch n88 reg_b[1] re clk 0
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.latch n93 reg_b[2] re clk 0
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.names b0 rst n83
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10 1
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.names b1 rst n88
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10 1
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.names b2 rst n93
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10 1
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.names b3 rst n33
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10 1
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.names cin rst n38
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10 1
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.names rst reg_b[2] reg_a[2] reg_b[3] reg_a[3] n67 n43
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0111-- 1
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011-1- 1
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01-1-0 1
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01--10 1
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0-11-0 1
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0-1-10 1
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0--11- 1
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.names reg_b[1] reg_cin reg_b[0] reg_a[0] reg_a[1] n67
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000-- 1
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00-0- 1
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0-00- 1
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0---0 1
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-00-0 1
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-0-00 1
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--000 1
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.names reg_cin reg_b[0] reg_a[0] rst n47
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0010 1
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0100 1
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1000 1
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1110 1
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.names reg_b[1] reg_a[1] rst reg_cin reg_b[0] reg_a[0] n51
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00011- 1
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0001-1 1
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000-11 1
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01000- 1
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0100-0 1
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010-00 1
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10000- 1
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1000-0 1
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100-00 1
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11011- 1
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1101-1 1
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110-11 1
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.names reg_b[2] reg_a[2] n67 rst n55
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0000 1
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0110 1
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1010 1
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1100 1
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.names reg_b[3] reg_a[3] rst reg_b[2] reg_a[2] n67 n59
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00011- 1
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0001-0 1
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000-10 1
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01000- 1
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0100-1 1
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010-01 1
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10000- 1
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1000-1 1
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100-01 1
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11011- 1
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1101-0 1
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110-10 1
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.names a0 rst n63
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10 1
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.names a1 rst n68
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10 1
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.names a2 rst n73
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10 1
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.names a3 rst n78
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10 1
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.end
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@ -0,0 +1,90 @@
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////////////////////////////////////////
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// //
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// Synchronized adder benchmark //
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// //
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////////////////////////////////////////
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module sync_4bits_add(
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clk,
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rst,
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a0,
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a1,
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a2,
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a3,
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b0,
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b1,
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b2,
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b3,
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cin,
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sumout0,
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sumout1,
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sumout2,
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sumout3,
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cout);
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input clk;
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input rst;
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input a0;
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input a1;
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input a2;
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input a3;
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input b0;
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input b1;
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input b2;
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input b3;
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input cin;
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output sumout0;
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output sumout1;
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output sumout2;
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output sumout3;
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output reg cout;
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wire[3:0] a;
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wire[3:0] b;
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reg[3:0] sumout;
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reg[3:0] reg_a;
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reg[3:0] reg_b;
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reg reg_cin;
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wire[4:0] int_sum;
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assign a[3] = a3;
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assign a[2] = a2;
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assign a[1] = a1;
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assign a[0] = a0;
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assign b[3] = b3;
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assign b[2] = b2;
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assign b[1] = b1;
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assign b[0] = b0;
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assign sumout3 = sumout[3];
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assign sumout2 = sumout[2];
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assign sumout1 = sumout[1];
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assign sumout0 = sumout[0];
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assign int_sum = reg_a + reg_b + reg_cin;
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always@(posedge clk or posedge rst) begin
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if(rst) begin
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reg_a <= 4'h0;
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reg_b <= 4'h0;
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reg_cin <= 1'h0;
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end
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else begin
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reg_a <= a;
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reg_b <= b;
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reg_cin <= cin;
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end
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end
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always@(posedge clk or posedge rst) begin
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if(rst) begin
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sumout <= 4'h0;
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cout <= 1'h0;
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end
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else begin
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sumout <= int_sum[3:0];
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cout <= int_sum[4];
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end
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end
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endmodule
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@ -1,7 +1,7 @@
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#!/bin/sh
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# Example of how to run vprset circuit_name = pip_add
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#set circuit_name = pip_add
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set circuit_name = fifo_1bit
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set circuit_name = sync_4bits_add
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set arch_file = ${PWD}/ARCH/k6_N10_scan_chain_tsmc40nm_TT.xml
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set circuit_blif = ${PWD}/Circuits/${circuit_name}.blif
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set circuit_act = ${PWD}/Circuits/${circuit_name}.act
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