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Include new files in the parameter spreading

This commit is contained in:
Baudouin Chauviere 2019-07-01 11:27:48 -06:00
parent 04eb6d3488
commit 0e04b88c8f
12 changed files with 117 additions and 75 deletions
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10
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c
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@ -3476,3 +3476,13 @@ int my_strlen_int(int input_int) {
return length_input;
}
boolean my_bool_to_boolean(bool my_bool) {
if(true == my_bool)
return TRUE;
if(false == my_bool)
return FALSE;
vpr_printf(TIO_MESSAGE_ERROR,"Failure to convert bool to boolean. Parameter is neither true nor false.\n");
exit(1);
}

1
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h
View File

@ -406,4 +406,5 @@ void get_fpga_x2p_global_all_clock_ports(t_llist* head,
int my_strlen_int(int input_int);
boolean my_bool_to_boolean(bool my_bool);
#endif

4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
View File

@ -282,7 +282,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
char* subckt_dir_path,
t_type_ptr phy_block_type,
int border_side,
boolean is_explicit_mapping) {
bool is_explicit_mapping) {
int iz;
int temp_reserved_conf_bits_msb;
int temp_iopad_lsb, temp_iopad_msb;
@ -515,7 +515,7 @@ void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir,
char* subckt_dir,
t_arch* arch,
boolean is_explicit_mapping) {
bool is_explicit_mapping) {
int itype, iside, num_sides;
int* stamped_spice_model_cnt = NULL;
t_sram_orgz_info* stamped_sram_orgz_info = NULL;

4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h
View File

@ -6,13 +6,13 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
char* subckt_dir_path,
t_type_ptr phy_block_type,
int border_side,
boolean is_explicit_mapping);
bool is_explicit_mapping);
void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir,
char* subckt_dir,
t_arch* arch,
boolean is_explicit_mapping);
bool is_explicit_mapping);
void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info,
char* circuit_name,

40
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
View File

@ -1038,7 +1038,7 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info,
enum e_spice_pin2pin_interc_type pin2pin_interc_type,
t_pb_graph_pin* des_pb_graph_pin,
t_mode* cur_mode,
boolean is_explicit_mapping) {
bool is_explicit_mapping) {
int iedge, ipin;
int fan_in = 0;
t_interconnect* cur_interc = NULL;
@ -1276,7 +1276,7 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "%s %s_%d_ ( ",
mem_subckt_name, mem_subckt_name, cur_interc->spice_model->cnt);
dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, cur_interc->spice_model, fan_in,
mem_model, cur_num_sram, cur_num_sram + num_mux_conf_bits - 1);
mem_model, cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, is_explicit_mapping);
fprintf(fp, ");\n");
/* update the number of memory bits */
update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_mux_conf_bits);
@ -1321,7 +1321,7 @@ void dump_verilog_pb_graph_port_interc(t_sram_orgz_info* cur_sram_orgz_info,
t_pb_graph_node* cur_pb_graph_node,
enum e_spice_pb_port_type pb_port_type,
t_mode* cur_mode,
boolean is_explicit_mapping) {
bool is_explicit_mapping) {
int iport, ipin;
/* Check the file handler*/
@ -1386,7 +1386,7 @@ void dump_verilog_pb_graph_interc(t_sram_orgz_info* cur_sram_orgz_info,
char* pin_prefix,
t_pb_graph_node* cur_pb_graph_node,
int select_mode_index,
boolean is_explicit_mapping) {
bool is_explicit_mapping) {
int ipb, jpb;
t_mode* cur_mode = NULL;
t_pb_type* cur_pb_type = cur_pb_graph_node->pb_type;
@ -1527,7 +1527,8 @@ void dump_verilog_pb_primitive_verilog_model(t_sram_orgz_info* cur_sram_orgz_inf
char* subckt_prefix,
t_pb_graph_node* prim_pb_graph_node,
int pb_index,
t_spice_model* verilog_model) {
t_spice_model* verilog_model,
bool is_explicit_mapping) {
/* Check the file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n",
@ -1551,23 +1552,27 @@ void dump_verilog_pb_primitive_verilog_model(t_sram_orgz_info* cur_sram_orgz_inf
case SPICE_MODEL_LUT:
/* If this is a idle block we should set sram_bits to zero*/
dump_verilog_pb_primitive_lut(cur_sram_orgz_info, fp, subckt_prefix, prim_pb_graph_node,
pb_index, verilog_model);
pb_index, verilog_model,
my_bool_to_boolean(is_explicit_mapping));
break;
case SPICE_MODEL_FF:
assert(NULL != verilog_model->model_netlist);
/* TODO : We should learn trigger type and initial value!!! and how to apply them!!! */
dump_verilog_pb_generic_primitive(cur_sram_orgz_info, fp, subckt_prefix, prim_pb_graph_node,
pb_index, verilog_model);
pb_index, verilog_model,
my_bool_to_boolean(is_explicit_mapping));
break;
case SPICE_MODEL_IOPAD:
assert(NULL != verilog_model->model_netlist);
dump_verilog_pb_generic_primitive (cur_sram_orgz_info, fp, subckt_prefix, prim_pb_graph_node,
pb_index, verilog_model);
pb_index, verilog_model,
my_bool_to_boolean(is_explicit_mapping));
break;
case SPICE_MODEL_HARDLOGIC:
assert(NULL != verilog_model->model_netlist);
dump_verilog_pb_generic_primitive(cur_sram_orgz_info, fp, subckt_prefix, prim_pb_graph_node,
pb_index, verilog_model);
pb_index, verilog_model,
my_bool_to_boolean(is_explicit_mapping));
break;
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of verilog_model(%s), should be [LUT|FF|HARD_LOGIC|IO]!\n",
@ -1587,7 +1592,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
char* subckt_prefix,
t_pb_graph_node* cur_pb_graph_node,
int pb_type_index,
boolean is_explicit_mapping) {
bool is_explicit_mapping) {
int mode_index, ipb, jpb, child_mode_index;
t_pb_type* cur_pb_type = NULL;
char* subckt_name = NULL;
@ -1668,21 +1673,24 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
case LUT_CLASS:
dump_verilog_pb_primitive_verilog_model(cur_sram_orgz_info, fp, formatted_subckt_prefix,
cur_pb_graph_node, pb_type_index,
cur_pb_type->spice_model); /* last param means idle */
cur_pb_type->spice_model,
my_bool_to_boolean(is_explicit_mapping)); /* last param means idle */
break;
case LATCH_CLASS:
assert(0 == cur_pb_type->num_modes);
/* Consider the num_pb, create all the subckts*/
dump_verilog_pb_primitive_verilog_model(cur_sram_orgz_info, fp, formatted_subckt_prefix,
cur_pb_graph_node, pb_type_index,
cur_pb_type->spice_model); /* last param means idle */
cur_pb_type->spice_model,
my_bool_to_boolean(is_explicit_mapping)); /* last param means idle */
break;
case UNKNOWN_CLASS:
case MEMORY_CLASS:
/* Consider the num_pb, create all the subckts*/
dump_verilog_pb_primitive_verilog_model(cur_sram_orgz_info, fp, formatted_subckt_prefix,
cur_pb_graph_node , pb_type_index,
cur_pb_type->spice_model); /* last param means idle */
cur_pb_type->spice_model,
my_bool_to_boolean(is_explicit_mapping)); /* last param means idle */
break;
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Unknown class type of pb_type(%s)!\n",
@ -1961,7 +1969,7 @@ void dump_verilog_physical_block(t_sram_orgz_info* cur_sram_orgz_info,
int y,
int z,
t_type_ptr type_descriptor,
boolean is_explicit_mapping) {
bool is_explicit_mapping) {
t_pb_graph_node* top_pb_graph_node = NULL;
t_block* mapped_block = NULL;
t_pb* top_pb = NULL;
@ -2476,7 +2484,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info,
char* subckt_dir,
int ix, int iy,
t_arch* arch,
boolean is_explicit_mapping) {
bool is_explicit_mapping) {
int subckt_name_str_len = 0;
char* subckt_name = NULL;
int iz;
@ -2701,7 +2709,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info,
void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info,
char* subckt_dir,
t_arch* arch,
boolean is_explicit_mapping) {
bool is_explicit_mapping) {
int ix, iy;
/* Check the grid*/

14
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h
View File

@ -59,14 +59,14 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info,
enum e_spice_pin2pin_interc_type pin2pin_interc_type,
t_pb_graph_pin* des_pb_graph_pin,
t_mode* cur_mode,
boolean is_explicit_mapping);
bool is_explicit_mapping);
void dump_verilog_pb_graph_interc(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
char* pin_prefix,
t_pb_graph_node* cur_pb_graph_node,
int select_mode_index,
boolean is_explicit_mapping);
bool is_explicit_mapping);
void dump_verilog_pb_graph_primitive_node(FILE* fp,
char* subckt_prefix,
@ -80,14 +80,14 @@ void dump_verilog_pb_primitive_verilog_model(t_sram_orgz_info* cur_sram_orgz_inf
t_pb_graph_node* prim_pb_graph_node,
int pb_index,
t_spice_model* verilog_model,
int is_idle);
bool is_explicit_mapping);
void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
char* subckt_prefix,
t_pb_graph_node* cur_pb_graph_node,
int pb_type_index,
boolean is_explicit_mapping);
bool is_explicit_mapping);
void dump_verilog_block(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
@ -105,7 +105,7 @@ void dump_verilog_physical_block(t_sram_orgz_info* cur_sram_orgz_info,
int y,
int z,
t_type_ptr type_descriptor,
boolean is_explicit_mapping);
bool is_explicit_mapping);
void dump_verilog_grid_pins(FILE* fp,
int x, int y,
@ -143,7 +143,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
int ix, int iy,
t_arch* arch,
boolean is_explicit_mapping);
bool is_explicit_mapping);
void dump_verilog_idle_block(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
@ -153,7 +153,7 @@ void dump_verilog_idle_block(t_sram_orgz_info* cur_sram_orgz_info,
void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info,
char* subckt_dir, t_arch* arch,
boolean is_explicit_mapping);
bool is_explicit_mapping);
void rec_copy_name_mux_in_node(t_pb_graph_node* master_node,
t_pb_graph_node* target_node);

18
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c
View File

@ -43,7 +43,8 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
char* subckt_prefix,
t_pb_graph_node* prim_pb_graph_node,
int index,
t_spice_model* verilog_model) {
t_spice_model* verilog_model,
bool is_explicit_mapping) {
int num_pad_port = 0; /* INOUT port */
t_spice_model_port** pad_ports = NULL;
int num_input_port = 0;
@ -122,7 +123,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "\n");
/* Only dump the global ports belonging to a spice_model
*/
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
@ -228,7 +229,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
/* Only dump the global ports belonging to a spice_model
* Disable recursive here !
*/
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, TRUE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
@ -370,7 +371,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "%s %s_%d_ ( ",
mem_subckt_name, mem_subckt_name, verilog_model->cnt);
dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, verilog_model, -1,
mem_model, cur_num_sram, cur_num_sram + num_sram - 1);
mem_model, cur_num_sram, cur_num_sram + num_sram - 1, my_bool_to_boolean(is_explicit_mapping));
fprintf(fp, ");\n");
/* update the number of memory bits */
update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_sram);
@ -404,7 +405,8 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
char* subckt_prefix,
t_pb_graph_node* prim_pb_graph_node,
int index,
t_spice_model* verilog_model) {
t_spice_model* verilog_model,
bool is_explicit_mapping) {
int i;
int lut_size = 0;
int num_input_port = 0;
@ -525,7 +527,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
formatted_subckt_prefix, cur_pb_type->name);
fprintf(fp, "\n");
/* Only dump the global ports belonging to a spice_model */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
/* Print inputs, outputs, inouts, clocks, NO SRAMs*/
@ -602,7 +604,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
* Only dump the global ports belonging to a spice_model
* DISABLE recursive here !
*/
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
/* Connect inputs*/
@ -680,7 +682,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "%s %s_%d_ ( ",
mem_subckt_name, mem_subckt_name, verilog_model->cnt);
dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, verilog_model, -1,
mem_model, cur_num_sram, cur_num_sram + num_sram - 1);
mem_model, cur_num_sram, cur_num_sram + num_sram - 1, is_explicit_mapping);
fprintf(fp, ");\n");
/* update the number of memory bits */
update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_sram);

6
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.h
View File

@ -5,11 +5,13 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
char* subckt_prefix,
t_pb_graph_node* prim_pb_graph_node,
int index,
t_spice_model* spice_model);
t_spice_model* spice_model,
bool is_explicit_mapping);
void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
char* subckt_prefix,
t_pb_graph_node* prim_pb_graph_node,
int index,
t_spice_model* spice_model);
t_spice_model* spice_model,
bool is_explicit_mapping);

65
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
View File

@ -695,7 +695,7 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
int mux_size,
t_rr_node** drive_rr_nodes,
int switch_index,
boolean is_explicit_mapping) {
bool is_explicit_mapping) {
int inode, side, index, input_cnt = 0;
int grid_x, grid_y;
t_spice_model* verilog_model = NULL;
@ -824,15 +824,27 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
verilog_model->prefix, mux_size, verilog_model->cnt);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
fprintf(fp, "%s_size%d_%d_inbus, ",
if (true == is_explicit_mapping) {
fprintf(fp, ".in(");
}
fprintf(fp, "%s_size%d_%d_inbus",
verilog_model->prefix, mux_size, verilog_model->cnt);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, " ,");
/* Output port */
if (true == is_explicit_mapping) {
fprintf(fp, ".out(");
}
dump_verilog_switch_box_chan_port(fp, cur_sb_info, chan_side, cur_rr_node, OUT_PORT);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
/* Add a comma because dump_verilog_switch_box_chan_port does not add so */
fprintf(fp, ", ");
@ -904,7 +916,8 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "%s %s_%d_ ( ",
mem_subckt_name, mem_subckt_name, verilog_model->cnt);
dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, verilog_model, mux_size, mem_model,
cur_num_sram, cur_num_sram + num_mux_conf_bits - 1);
cur_num_sram, cur_num_sram + num_mux_conf_bits - 1,
my_bool_to_boolean(is_explicit_mapping));
fprintf(fp, ");\n");
/* update the number of memory bits */
update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_mux_conf_bits);
@ -945,7 +958,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
int mux_size,
t_rr_node** drive_rr_nodes,
int switch_index,
boolean is_explicit_mapping) {
bool is_explicit_mapping) {
int input_cnt = 0;
t_spice_model* verilog_model = NULL;
int mux_level, path_id, cur_num_sram;
@ -1067,7 +1080,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
verilog_model->prefix, mux_size, verilog_model->cnt);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, is_explicit_mapping)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
@ -1158,8 +1171,10 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
mem_subckt_name = generate_verilog_mux_subckt_name(verilog_model, mux_size, verilog_mem_posfix);
fprintf(fp, "%s %s_%d_ ( ",
mem_subckt_name, mem_subckt_name, verilog_model->cnt);
dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, verilog_model, mux_size, mem_model,
cur_num_sram, cur_num_sram + num_mux_conf_bits - 1);
dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info,
verilog_model, mux_size, mem_model,
cur_num_sram, cur_num_sram + num_mux_conf_bits - 1,
is_explicit_mapping);
fprintf(fp, ");\n");
/* update the number of memory bits */
update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_mux_conf_bits);
@ -1345,7 +1360,7 @@ void dump_verilog_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
t_sb* cur_sb_info,
int chan_side,
t_rr_node* cur_rr_node,
boolean is_explicit_mapping) {
bool is_explicit_mapping) {
int sb_x, sb_y;
int num_drive_rr_nodes = 0;
t_rr_node** drive_rr_nodes = NULL;
@ -1403,7 +1418,7 @@ void dump_verilog_unique_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
const RRGSB& rr_sb,
enum e_side chan_side,
size_t chan_node_id,
boolean is_explicit_mapping) {
bool is_explicit_mapping) {
int num_drive_rr_nodes = 0;
t_rr_node** drive_rr_nodes = NULL;
@ -1801,7 +1816,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr
char* verilog_dir, char* subckt_dir,
size_t module_id, size_t seg_id,
const RRGSB& rr_sb, enum e_side side,
boolean is_explicit_mapping) {
bool is_explicit_mapping) {
FILE* fp = NULL;
char* fname = NULL;
Side side_manager(side);
@ -2190,7 +2205,7 @@ static
void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir, char* subckt_dir,
const RRGSB& rr_sb,
boolean is_explicit_mapping) {
bool is_explicit_mapping) {
FILE* fp = NULL;
char* fname = NULL;
@ -2372,7 +2387,7 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info
char* verilog_dir, char* subckt_dir,
t_sb* cur_sb_info,
boolean compact_routing_hierarchy,
boolean is_explicit_mapping) {
bool is_explicit_mapping) {
int itrack, inode, side, ix, iy, x, y;
int cur_num_sram, num_conf_bits, num_reserved_conf_bits, esti_sram_cnt;
FILE* fp = NULL;
@ -2791,7 +2806,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
const RRGSB& rr_gsb, t_rr_type cb_type,
t_rr_node* src_rr_node,
boolean is_explicit_mapping) {
bool is_explicit_mapping) {
int mux_size, cur_num_sram, input_cnt = 0;
t_rr_node** drive_rr_nodes = NULL;
int mux_level, path_id, switch_index;
@ -2904,7 +2919,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
verilog_model->prefix, mux_size, verilog_model->cnt);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
@ -2985,7 +3000,8 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "%s %s_%d_ ( ",
mem_subckt_name, mem_subckt_name, verilog_model->cnt);
dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, verilog_model, mux_size, mem_model,
cur_num_sram, cur_num_sram + num_mux_conf_bits - 1);
cur_num_sram, cur_num_sram + num_mux_conf_bits - 1,
my_bool_to_boolean(is_explicit_mapping));
fprintf(fp, ");\n");
/* update the number of memory bits */
update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_mux_conf_bits);
@ -3021,7 +3037,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
t_cb* cur_cb_info,
t_rr_node* src_rr_node,
boolean is_explicit_mapping) {
bool is_explicit_mapping) {
int mux_size, cur_num_sram, input_cnt = 0;
t_rr_node** drive_rr_nodes = NULL;
int inode, mux_level, path_id, switch_index;
@ -3137,7 +3153,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
verilog_model->prefix, mux_size, verilog_model->cnt);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
@ -3218,7 +3234,8 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "%s %s_%d_ ( ",
mem_subckt_name, mem_subckt_name, verilog_model->cnt);
dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, verilog_model, mux_size, mem_model,
cur_num_sram, cur_num_sram + num_mux_conf_bits - 1);
cur_num_sram, cur_num_sram + num_mux_conf_bits - 1,
my_bool_to_boolean(is_explicit_mapping));
fprintf(fp, ");\n");
/* update the number of memory bits */
update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_mux_conf_bits);
@ -3253,7 +3270,7 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
const RRGSB& rr_gsb, t_rr_type cb_type,
t_rr_node* src_rr_node,
boolean is_explicit_mapping) {
bool is_explicit_mapping) {
/* Check the file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n",
@ -3278,7 +3295,7 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
t_cb* cur_cb_info,
t_rr_node* src_rr_node,
boolean is_explicit_mapping) {
bool is_explicit_mapping) {
/* Check the file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n",
@ -3422,7 +3439,7 @@ static
void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir, char* subckt_dir,
const RRGSB& rr_cb, t_rr_type cb_type,
boolean is_explicit_mapping) {
bool is_explicit_mapping) {
FILE* fp = NULL;
char* fname = NULL;
int cur_num_sram, num_conf_bits, num_reserved_conf_bits, esti_sram_cnt;
@ -3587,7 +3604,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_
char* verilog_dir, char* subckt_dir,
t_cb* cur_cb_info,
boolean compact_routing_hierarchy,
boolean is_explicit_mapping) {
bool is_explicit_mapping) {
int itrack, inode, side, x, y;
int side_cnt = 0;
FILE* fp = NULL;

12
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h
View File

@ -41,7 +41,7 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
int mux_size,
t_rr_node** drive_rr_nodes,
int switch_index,
boolean is_explicit_mapping);
bool is_explicit_mapping);
int count_verilog_switch_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
t_sb cur_sb_info, int chan_side,
@ -56,7 +56,7 @@ void dump_verilog_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
t_sb* cur_sb_info,
int chan_side,
t_rr_node* cur_rr_node,
boolean is_explicit_mapping);
bool is_explicit_mapping);
int count_verilog_switch_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
t_sb cur_sb_info);
@ -71,7 +71,7 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info
t_ivec*** LL_rr_node_indices,
t_syn_verilog_opts fpga_verilog_opts,
boolean compact_routing_hierarchy,
boolean is_explicit_mapping);
bool is_explicit_mapping);
void dump_verilog_connection_box_short_interc(FILE* fp,
@ -82,13 +82,13 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
t_cb* cur_cb_info,
t_rr_node* src_rr_node,
boolean is_explicit_mapping);
bool is_explicit_mapping);
void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
t_cb* cur_cb_info,
t_rr_node* src_rr_node,
boolean is_explicit_mapping);
bool is_explicit_mapping);
int count_verilog_connection_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
@ -127,7 +127,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_
char* verilog_dir, char* subckt_dir,
t_cb* cur_cb_info,
boolean compact_routing_hierarchy,
boolean is_explicit_mapping);
bool is_explicit_mapping);
void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,

11
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c
View File

@ -2550,7 +2550,7 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m
int mux_size, int cur_num_sram,
int num_mux_reserved_conf_bits,
int num_mux_conf_bits,
boolean is_explicit_mapping) {
bool is_explicit_mapping) {
/* Check the file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n",
@ -2570,7 +2570,7 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m
/* FOR Scan-chain, we need regular output of a scan-chain FF
* We do not need a prefix implying MUX name, size and index
*/
if (TRUE == is_explicit_mapping) {
if (true == is_explicit_mapping) {
fprintf(fp, ".sram(");
}
dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info,
@ -2638,7 +2638,7 @@ void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model,
int mux_size, int cur_num_sram,
int num_mux_reserved_conf_bits,
int num_mux_conf_bits,
boolean is_explicit_mapping) {
bool is_explicit_mapping) {
/* Check the file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n",
@ -3058,7 +3058,8 @@ void dump_verilog_mem_sram_submodule(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
t_spice_model* cur_verilog_model, int mux_size,
t_spice_model* cur_sram_verilog_model,
int lsb, int msb) {
int lsb, int msb,
bool is_explicit_mapping) {
int cur_bl, cur_wl;
int num_bl_ports, num_wl_ports;
t_spice_model_port** bl_port = NULL;
@ -3106,7 +3107,7 @@ void dump_verilog_mem_sram_submodule(FILE* fp,
}
/* Only dump the global ports belonging to a spice_model */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}

7
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h
View File

@ -188,14 +188,14 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m
int mux_size, int cur_num_sram,
int num_mux_reserved_conf_bits,
int num_mux_conf_bits,
boolean is_explicit_mapping);
bool is_explicit_mapping);
void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model,
t_sram_orgz_info* cur_sram_orgz_info,
int mux_size, int cur_num_sram,
int num_mux_reserved_conf_bits,
int num_mux_conf_bits,
boolean is_explicit_mapping);
bool is_explicit_mapping);
void dump_verilog_grid_common_port(FILE* fp, t_spice_model* cur_verilog_model,
char* general_port_prefix, int lsb, int msb,
@ -239,7 +239,8 @@ void dump_verilog_mem_sram_submodule(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
t_spice_model* cur_verilog_model, int mux_size,
t_spice_model* cur_sram_verilog_model,
int lsb, int msb);
int lsb, int msb,
bool is_explicit_mapping);
char* gen_verilog_grid_one_pin_name(int x, int y,
int height, int side, int pin_index,