Avoid configuration bits for module wihch don't require them

2019-06-20 09:40:41 -06:00 · 2019-06-20 09:40:41 -06:00 · a7502bb43b
parent ff00e4c79c
commit a7502bb43b
1 changed files with 3 additions and 1 deletions
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
@ -1767,9 +1767,11 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
  /* Definition ends*/

  /* Local wires for memory configurations */
-  dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info, 
+  if (0 < num_conf_bits) { 
+    dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info, 
                                              stamped_sram_cnt, 
                                              stamped_sram_cnt + num_conf_bits - 1); 
+  }

  /* Quote all child pb_types */
  for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) {