From a7502bb43b0fc8bd0f78fd1735ee0a054bc7ce3d Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Thu, 20 Jun 2019 09:40:41 -0600 Subject: [PATCH] Avoid configuration bits for module wihch don't require them --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c index e3bdbf332..ea01fc03e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c @@ -1767,9 +1767,11 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, /* Definition ends*/ /* Local wires for memory configurations */ - dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info, + if (0 < num_conf_bits) { + dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info, stamped_sram_cnt, stamped_sram_cnt + num_conf_bits - 1); + } /* Quote all child pb_types */ for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) {