developing ipin2track mapping for tiles
This commit is contained in:
tangxifan
parent
9ca1b42f4c
commit
ba15358564
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@ -56,7 +56,7 @@
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#include "ReadOptions.h"
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#include "rr_graph.h"
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#include "rr_graph2.h"
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#include "rr_graph_sbox.h"
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#include "rr_graph_tileable_sbox.h"
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#include "route_common.h"
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#include "fpga_x2p_types.h"
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#include "rr_graph_tileable_builder.h"
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@ -1384,6 +1384,52 @@ void build_edges_for_one_tileable_rr_gsb(t_rr_graph* rr_graph, RRGSB* rr_gsb,
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return;
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}
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/************************************************************************
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* Convert the track_to_ipin_look[0..nodes_per_chan-1][0..height][0..3][pin_numbers]
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* to the existing routing resources in the General Switch Block (GSB)
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* The resulting matrix will be oragnized in
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* track2ipin_lookup[gsb_side][0..chan_width-1][ipin_indices]
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***********************************************************************/
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static
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std::vector < std::vector< std::vector<int> > > build_gsb_track_to_ipin_lookup(const RRGSB& rr_gsb,
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std::vector< std::vector<t_grid_tile> > grids,
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int** Fc_in,
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int***** ipin_to_track_map) {
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std::vector < std::vector< std::vector<int> > > track2ipin_lookup; /* [0..gsb_side][0..num_tracks][0..Fc-1] */
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/* Resize the matrix */
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track2ipin_lookup.resize(rr_gsb.get_num_sides());
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/* Walk through each side */
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for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
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Side side_manager(side);
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enum e_side gsb_side = side_manager.get_side();
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/* Get channel width and resize the matrix */
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size_t chan_width = rr_gsb.get_chan_width(gsb_side);
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track2ipin_lookup[side].resize(chan_width);
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/* Find the ipin nodes */
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for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(gsb_side); ++inode) {
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t_rr_node* ipin_node = rr_gsb.get_ipin_node(gsb_side, inode);
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/* For each IPIN, we find the type_descriptor, offset and pin_side on the grid */
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int grid_type_id = grids[ipin_node->xlow][ipin_node->ylow].type->index;
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int offset = grid[ipin_node->xlow][ipin_node->ylow].offset;
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enum e_side pin_side = rr_gsb.get_ipin_node_grid_side(gsb_side, inode);
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/* Now, we fill the return matrix */
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/* Bypass empty array */
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if (NULL == ipin_to_track_map[grid_type_id][ipin_node->ptc_num][offset][0]) {
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continue;
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}
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/* Get each track_id */
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for (int iconn = 0; iconn < Fc_in[grid_type_id][ipin_node->ptc_num]; ++iconn) {
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int track_id = ipin_to_track_map[grid_type_id][ipin_node->ptc_num][offset][pin_side][iconn];
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track2ipin_lookup[gsb_side][track_id].push_back(inode);
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}
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}
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}
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return track2ipin_lookup;
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}
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/************************************************************************
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* Build the edges of each rr_node tile by tile:
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* We classify rr_nodes into a general switch block (GSB) data structure
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@ -1399,10 +1445,12 @@ void build_edges_for_one_tileable_rr_gsb(t_rr_graph* rr_graph, RRGSB* rr_gsb,
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static
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void build_rr_graph_edges(t_rr_graph* rr_graph,
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const DeviceCoordinator& device_size,
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std::vector< std::vector<t_grid_tile> > grids,
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std::vector<size_t> device_chan_width,
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std::vector<t_segment_inf> segment_inf,
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int L_num_types, t_type_ptr types,
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struct s_ivec**** track_to_ipin_lookup, int***** opin_to_track_map,
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int** Fc_in, int** Fc_out,
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int***** ipin_to_track_map, int***** opin_to_track_map,
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vtr::NdMatrix<std::vector<int>,3> switch_block_conn,
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int num_directs, t_clb_to_clb_directs* clb_to_clb_directs,
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int num_switches, int delayless_switch) {
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@ -1414,11 +1462,12 @@ void build_rr_graph_edges(t_rr_graph* rr_graph,
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/* Create a GSB object */
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RRGSB rr_gsb = build_one_tileable_rr_gsb(device_range, device_chan_width, segment_inf, gsb_coordinator, rr_graph);
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/* adapt the track_to_ipin_lookup for the GSB nodes */
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std::vector < std::vector< std::vector<int> > > track2ipin_lookup; /* [0..gsb_side][0..num_tracks][0..Fc] */
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std::vector < std::vector< std::vector<int> > > track2ipin_lookup; /* [0..gsb_side][0..num_tracks][0..Fc-1] */
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track2ipin_lookup = build_gsb_track_to_ipin_lookup(rr_gsb, grids, Fc_in, ipin_to_track_map);
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/* adapt the opin_to_track_map for the GSB nodes */
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std::vector < std::vector< std::vector<int> > > opin2track_map; /* [0..gsb_side][0..num_opin_node][0..Fc] */
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std::vector < std::vector< std::vector<int> > > opin2track_map; /* [0..gsb_side][0..num_opin_node][0..Fc-1] */
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/* adapt the switch_block_conn for the GSB nodes */
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std::vector < std::vector< std::vector<int> > > sb_conn; /* [0..gsb_side][0..chan_width][0..Fc] */
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std::vector < std::vector< std::vector<int> > > sb_conn; /* [0..from_gsb_side][0..to_gsb_side][0..chan_width-1] */
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/* Build edges for a GSB */
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build_edges_for_one_tileable_rr_gsb(rr_graph, &rr_gsb,
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track2ipin_lookup, opin2track_map, sb_conn,
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@ -1431,76 +1480,6 @@ void build_rr_graph_edges(t_rr_graph* rr_graph,
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return;
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}
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/************************************************************************
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* Build internal connection pattern for a switch block
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* This function is adapt to fit the tileable routing context from
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* rr_graph_sbox.c : alloc_and_load_switch_block_conn
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* Switch box: *
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* TOP (CHANY) *
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* | | | | | | *
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* +-----------+ *
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* --| |-- *
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* --| |-- *
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* LEFT --| |-- RIGHT *
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* (CHANX)--| |--(CHANX) *
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* --| |-- *
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* --| |-- *
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* +-----------+ *
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* | | | | | | *
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* BOTTOM (CHANY)
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*
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* [0..3][0..3][0..nodes_per_chan-1]. Structure below is indexed as: *
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* [from_side][to_side][from_track]. That yields an integer vector (ivec) *
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* of the tracks to which from_track connects in the proper to_location. *
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* For simple switch boxes this is overkill, but it will allow complicated *
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* switch boxes with Fs > 3, etc. without trouble.
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***********************************************************************/
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static
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vtr::NdMatrix<std::vector<int>,3> alloc_and_load_tileable_switch_block_conn(size_t chan_width,
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enum e_switch_block_type switch_block_type,
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int Fs) {
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/* Currently Fs must be 3 since each track maps once to each other side */
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VTR_ASSERT(3 == Fs);
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vtr::NdMatrix<std::vector<int>,3> switch_block_conn({4, 4, chan_width});
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for (e_side from_side : {TOP, RIGHT, BOTTOM, LEFT}) {
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for (e_side to_side : {TOP, RIGHT, BOTTOM, LEFT}) {
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for (size_t from_track = 0; from_track < chan_width; from_track++) {
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if (from_side != to_side) {
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switch_block_conn[from_side][to_side][from_track].resize(1);
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switch_block_conn[from_side][to_side][from_track][0] = get_simple_switch_block_track(from_side, to_side,
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from_track, switch_block_type,
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chan_width);
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} else { /* from_side == to_side -> no connection. */
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switch_block_conn[from_side][to_side][from_track].clear();
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}
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}
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}
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}
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if (getEchoEnabled()) {
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FILE *out = fopen("switch_block_conn.echo", "w");
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for (int l = 0; l < 4; ++l) {
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for (int k = 0; k < 4; ++k) {
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fprintf(out, "Side %d to %d\n", l, k);
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for (size_t j = 0; j < chan_width; ++j) {
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fprintf(out, "%zu: ", j);
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for (unsigned i = 0; i < switch_block_conn[l][k][j].size(); ++i) {
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fprintf(out, "%d ", switch_block_conn[l][k][j][i]);
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}
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fprintf(out, "\n");
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}
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fprintf(out, "\n");
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}
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}
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fclose(out);
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}
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return switch_block_conn;
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}
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/************************************************************************
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* Main function of this file
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* Builder for a detailed uni-directional tileable rr_graph
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@ -1646,13 +1625,10 @@ void build_tileable_unidir_rr_graph(INP int L_num_types,
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/* START IPINP MAP */
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/* Create ipin map lookups */
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int***** ipin_to_track_map = (int*****) my_calloc(L_num_types, sizeof(int****));
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struct s_ivec**** track_to_ipin_lookup = (struct s_ivec****) my_calloc(L_num_types, sizeof(struct s_ivec***));
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boolean* perturb_ipins = alloc_and_load_perturb_ipins(chan_width, L_num_types, Fc_in, Fc_out, UNI_DIRECTIONAL);
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for (int i = 0; i < L_num_types; ++i) {
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ipin_to_track_map[i] = alloc_and_load_pin_to_track_map(RECEIVER, chan_width, Fc_in[i], &types[i],
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perturb_ipins[i], UNI_DIRECTIONAL);
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track_to_ipin_lookup[i] = alloc_and_load_track_to_pin_lookup(ipin_to_track_map[i], Fc_in[i],
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types[i].height, types[i].num_pins, chan_width);
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}
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/* END IPINP MAP */
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@ -1683,8 +1659,8 @@ void build_tileable_unidir_rr_graph(INP int L_num_types,
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}
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/* Create edges for a tileable rr_graph */
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build_rr_graph_edges(&rr_graph, device_size, device_chan_width, segment_infs,
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L_num_types, types, track_to_ipin_lookup, opin_to_track_map, switch_block_conn,
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build_rr_graph_edges(&rr_graph, device_size, grids, device_chan_width, segment_infs,
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L_num_types, types, Fc_in, Fc_out, ipin_to_track_map, opin_to_track_map, switch_block_conn,
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num_directs, clb_to_clb_directs, num_switches, delayless_switch);
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/************************************************************************
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@ -1731,7 +1707,6 @@ void build_tileable_unidir_rr_graph(INP int L_num_types,
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}
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free_type_pin_to_track_map(ipin_to_track_map, types);
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free_type_track_to_ipin_map(track_to_ipin_lookup, types, chan_width);
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if(clb_to_clb_directs != NULL) {
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free(clb_to_clb_directs);
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}
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@ -0,0 +1,211 @@
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#include "vtr_assert.h"
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#include "vtr_util.h"
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#include "vtr_memory.h"
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#include "vpr_types.h"
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#include "rr_graph_tileable_sbox.h"
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#include "rr_graph_util.h"
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#include "ReadOptions.h"
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static
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int get_tileable_simple_switch_block_track(const enum e_side from_side,
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const enum e_side to_side, const int from_track,
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const enum e_switch_block_type switch_block_type, const int nodes_per_chan);
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/************************************************************************
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* Build internal connection pattern for a switch block
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* This function is adapt to fit the tileable routing context from
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* rr_graph_sbox.c : alloc_and_load_switch_block_conn
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* Switch box: *
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* TOP (CHANY) *
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* | | | | | | *
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* +-----------+ *
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* --| |-- *
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* --| |-- *
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* LEFT --| |-- RIGHT *
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* (CHANX)--| |--(CHANX) *
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* --| |-- *
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* --| |-- *
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* +-----------+ *
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* | | | | | | *
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* BOTTOM (CHANY) *
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*
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* [0..3][0..3][0..nodes_per_chan-1]. Structure below is indexed as: *
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* [from_side][to_side][from_track]. That yields an integer vector (ivec) *
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* of the tracks to which from_track connects in the proper to_location. *
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* For simple switch boxes this is overkill, but it will allow complicated *
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* switch boxes with Fs > 3, etc. without trouble. *
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***********************************************************************/
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/* Allocates and loads the switch_block_conn data structure. This structure *
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* lists which tracks connect to which at each switch block. This is for
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* bidir. */
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vtr::NdMatrix<std::vector<int>,3> alloc_and_load_tileable_switch_block_conn(const size_t nodes_per_chan,
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const e_switch_block_type switch_block_type,
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const int Fs) {
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/* Currently Fs must be 3 since each track maps once to each other side */
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VTR_ASSERT(3 == Fs);
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vtr::NdMatrix<std::vector<int>,3> switch_block_conn({4, 4, nodes_per_chan});
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for (e_side from_side : {TOP, RIGHT, BOTTOM, LEFT}) {
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for (e_side to_side : {TOP, RIGHT, BOTTOM, LEFT}) {
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for (size_t from_track = 0; from_track < nodes_per_chan; from_track++) {
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if (from_side != to_side) {
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switch_block_conn[from_side][to_side][from_track].resize(1);
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switch_block_conn[from_side][to_side][from_track][0] = get_tileable_simple_switch_block_track(from_side, to_side,
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from_track, switch_block_type, nodes_per_chan);
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} else { /* from_side == to_side -> no connection. */
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switch_block_conn[from_side][to_side][from_track].clear();
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}
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}
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}
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}
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if (getEchoEnabled()) {
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FILE *out = vtr::fopen("switch_block_conn.echo", "w");
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for (int l = 0; l < 4; ++l) {
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for (int k = 0; k < 4; ++k) {
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fprintf(out, "Side %d to %d\n", l, k);
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for (size_t j = 0; j < nodes_per_chan; ++j) {
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fprintf(out, "%zu: ", j);
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for (unsigned i = 0; i < switch_block_conn[l][k][j].size(); ++i) {
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fprintf(out, "%d ", switch_block_conn[l][k][j][i]);
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}
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fprintf(out, "\n");
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}
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fprintf(out, "\n");
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}
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}
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fclose(out);
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}
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return switch_block_conn;
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}
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#define SBOX_ERROR -1
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/* This routine permutes the track number to connect for topologies
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* SUBSET, UNIVERSAL, and WILTON. I added FULL (for fully flexible topology)
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* but the returned value is simply a dummy, since we don't need to permute
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* what connections to make for FULL (connect to EVERYTHING) */
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static
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int get_tileable_simple_switch_block_track(const enum e_side from_side,
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const enum e_side to_side, const int from_track,
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const enum e_switch_block_type switch_block_type, const int nodes_per_chan) {
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/* This routine returns the track number to which the from_track should *
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* connect. It supports three simple, Fs = 3, switch blocks. */
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int to_track = SBOX_ERROR; /* Can check to see if it's not set later. */
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if (switch_block_type == SUBSET) { /* NB: Global routing uses SUBSET too */
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to_track = from_track;
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}
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/* See S. Wilton Phd thesis, U of T, 1996 p. 103 for details on following. */
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else if (switch_block_type == WILTON) {
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if (from_side == LEFT) {
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if (to_side == RIGHT) { /* CHANX to CHANX */
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to_track = from_track;
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} else if (to_side == TOP) { /* from CHANX to CHANY */
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to_track = (nodes_per_chan - (from_track % nodes_per_chan)) % nodes_per_chan;
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} else if (to_side == BOTTOM) {
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to_track = (nodes_per_chan + from_track - 1) % nodes_per_chan;
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}
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}
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else if (from_side == RIGHT) {
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if (to_side == LEFT) { /* CHANX to CHANX */
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to_track = from_track;
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} else if (to_side == TOP) { /* from CHANX to CHANY */
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to_track = (nodes_per_chan + from_track - 1) % nodes_per_chan;
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} else if (to_side == BOTTOM) {
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to_track = (2 * nodes_per_chan - 2 - from_track) % nodes_per_chan;
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}
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}
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else if (from_side == BOTTOM) {
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if (to_side == TOP) { /* CHANY to CHANY */
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to_track = from_track;
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} else if (to_side == LEFT) { /* from CHANY to CHANX */
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to_track = (from_track + 1) % nodes_per_chan;
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} else if (to_side == RIGHT) {
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to_track = (2 * nodes_per_chan - 2 - from_track) % nodes_per_chan;
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}
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}
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else if (from_side == TOP) {
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if (to_side == BOTTOM) { /* CHANY to CHANY */
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to_track = from_track;
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} else if (to_side == LEFT) { /* from CHANY to CHANX */
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to_track = (nodes_per_chan - (from_track % nodes_per_chan)) % nodes_per_chan;
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} else if (to_side == RIGHT) {
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to_track = (from_track + 1) % nodes_per_chan;
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}
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}
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/* Force to_track to UN_SET if it falls outside the min/max channel width range */
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if (to_track < 0 || to_track >= nodes_per_chan) {
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to_track = -1;
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}
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}
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/* End switch_block_type == WILTON case. */
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else if (switch_block_type == UNIVERSAL) {
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if (from_side == LEFT) {
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if (to_side == RIGHT) { /* CHANX to CHANX */
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to_track = from_track;
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} else if (to_side == TOP) { /* from CHANX to CHANY */
|
||||
to_track = nodes_per_chan - 1 - from_track;
|
||||
} else if (to_side == BOTTOM) {
|
||||
to_track = from_track;
|
||||
}
|
||||
}
|
||||
|
||||
else if (from_side == RIGHT) {
|
||||
if (to_side == LEFT) { /* CHANX to CHANX */
|
||||
to_track = from_track;
|
||||
} else if (to_side == TOP) { /* from CHANX to CHANY */
|
||||
to_track = from_track;
|
||||
} else if (to_side == BOTTOM) {
|
||||
to_track = nodes_per_chan - 1 - from_track;
|
||||
}
|
||||
}
|
||||
|
||||
else if (from_side == BOTTOM) {
|
||||
if (to_side == TOP) { /* CHANY to CHANY */
|
||||
to_track = from_track;
|
||||
} else if (to_side == LEFT) { /* from CHANY to CHANX */
|
||||
to_track = from_track;
|
||||
} else if (to_side == RIGHT) {
|
||||
to_track = nodes_per_chan - 1 - from_track;
|
||||
}
|
||||
}
|
||||
|
||||
else if (from_side == TOP) {
|
||||
if (to_side == BOTTOM) { /* CHANY to CHANY */
|
||||
to_track = from_track;
|
||||
} else if (to_side == LEFT) { /* from CHANY to CHANX */
|
||||
to_track = nodes_per_chan - 1 - from_track;
|
||||
} else if (to_side == RIGHT) {
|
||||
to_track = from_track;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* End switch_block_type == UNIVERSAL case. */
|
||||
/* UDSD Modification by WMF Begin */
|
||||
if (switch_block_type == FULL) { /* Just a placeholder. No meaning in reality */
|
||||
to_track = from_track;
|
||||
}
|
||||
/* UDSD Modification by WMF End */
|
||||
|
||||
return (to_track);
|
||||
}
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
#ifndef RR_GRAPH_TILEABLE_SBOX_H
|
||||
#define RR_GRAPH_TILEABLE_SBOX_H
|
||||
|
||||
#include <vector>
|
||||
|
||||
#include "vtr_ndmatrix.h"
|
||||
|
||||
vtr::NdMatrix<std::vector<int>,3> alloc_and_load_tileable_switch_block_conn(size_t nodes_per_chan,
|
||||
enum e_switch_block_type switch_block_type, int Fs);
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue