riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Correct manual testbench generation bug

This commit is contained in:
AurelienUoU 2019-01-07 18:03:56 -07:00
parent 5dbcfa6d70
commit b80e435548
1 changed files with 13 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_top_netlist.c
View File

@ -1640,11 +1640,19 @@ void dump_verilog_top_testbench_ports(FILE* fp,
assert((VPACK_INPAD == logical_block[iblock].type)||(VPACK_OUTPAD == logical_block[iblock].type));
fprintf(fp, "//----- Blif Benchmark inout %s is mapped to FPGA IOPAD %s[%d] -----\n",
logical_block[iblock].name, gio_inout_prefix, iopad_idx);
fprintf(fp, "wire in_%s_%s_%d_;\n",
logical_block[iblock].name, gio_inout_prefix, iopad_idx);
fprintf(fp, "assign in_%s_%s_%d_ = %s%s[%d];\n",
logical_block[iblock].name, gio_inout_prefix, iopad_idx,
gio_inout_prefix, iopad_verilog_model->prefix, iopad_idx);
if(VPACK_INPAD == logical_block[iblock].type){
fprintf(fp, "wire in_%s_%s_%d_;\n",
logical_block[iblock].name, gio_inout_prefix, iopad_idx);
fprintf(fp, "assign in_%s_%s_%d_ = %s%s[%d];\n",
logical_block[iblock].name, gio_inout_prefix, iopad_idx,
gio_inout_prefix, iopad_verilog_model->prefix, iopad_idx);
} else{
fprintf(fp, "wire %s_%s_%d_;\n",
logical_block[iblock].name, gio_inout_prefix, iopad_idx);
fprintf(fp, "assign %s_%s_%d_ = %s%s[%d];\n",
logical_block[iblock].name, gio_inout_prefix, iopad_idx,
gio_inout_prefix, iopad_verilog_model->prefix, iopad_idx);
}
}
}