Eddie Hung
a193bf27c9
Clean up trimming leading 1'bx in A during techmappnig
2019-06-28 12:03:43 -07:00
Eddie Hung
cf020befeb
Fix CARRY4 abc_box_id
2019-06-28 11:28:50 -07:00
Eddie Hung
4ef26d4755
Merge remote-tracking branch 'origin/master' into xc7mux
2019-06-28 11:09:42 -07:00
Eddie Hung
03705f69f4
Update synth_ice40 -device doc to be relevant for -abc9 only
2019-06-28 09:49:01 -07:00
Eddie Hung
3f87575cb6
Disable boxing of ECP5 dist RAM due to regression
2019-06-28 09:46:36 -07:00
Eddie Hung
0318860b93
Add write address to abc_scc_break of ECP5 dist RAM
2019-06-28 09:45:48 -07:00
Eddie Hung
b9ddee0c87
Fix DO4 typo
2019-06-28 09:45:40 -07:00
Eddie Hung
00f63d82ce
Reduce diff with upstream
2019-06-27 16:13:22 -07:00
Eddie Hung
af8a5ae5fe
Extraneous newline
2019-06-27 16:12:20 -07:00
Eddie Hung
4daa746797
Remove noise from ice40/cells_sim.v
2019-06-27 16:11:39 -07:00
Eddie Hung
9398921af1
Refactor for one "abc_carry" attribute on module
2019-06-27 16:07:14 -07:00
Eddie Hung
312c03e4ca
Remove redundant doc
2019-06-27 15:28:55 -07:00
Eddie Hung
4d00e27ed7
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-27 11:23:30 -07:00
Eddie Hung
1237a4c116
Add warning if synth_xilinx -abc9 with family != xc7
2019-06-27 11:22:49 -07:00
Eddie Hung
6c256b8cda
Merge origin/master
2019-06-27 11:20:15 -07:00
Eddie Hung
593e4a30bb
MUXF78 -> $__MUXF78 to indicate internal
2019-06-26 20:09:28 -07:00
Eddie Hung
dbb8c8caaa
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-26 20:07:31 -07:00
Eddie Hung
4de25a1949
Add WE to ECP5 dist RAM's abc_scc_break too
2019-06-26 20:02:19 -07:00
Eddie Hung
a7a88109f5
Update comment on boxes
2019-06-26 20:00:15 -07:00
Eddie Hung
b7bef15b16
Add "WE" to dist RAM's abc_scc_break
2019-06-26 19:58:09 -07:00
Eddie Hung
b9ff0503f3
synth_xilinx's muxcover call to be very conservative -- -nodecode
2019-06-26 17:57:10 -07:00
Eddie Hung
f0a1726a1a
Accidentally removed "simplemap $mux"
2019-06-26 17:48:49 -07:00
Eddie Hung
2b104ed6c8
Replace with <internal options>
2019-06-26 17:42:50 -07:00
Eddie Hung
cae69a3edd
Rework help_mode for synth_xilinx -widemux
2019-06-26 17:41:21 -07:00
Eddie Hung
5f807a7a5b
Return to upstream synth_xilinx with opt -full and wreduce
2019-06-26 16:25:48 -07:00
Eddie Hung
812469aaa3
Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux
2019-06-26 14:48:35 -07:00
Eddie Hung
c762be5930
Instead of blocking wreduce on $mux, use -keepdc instead #1132
2019-06-26 11:48:35 -07:00
Eddie Hung
8d8261c71f
Do not call opt with -full before muxcover
2019-06-26 11:38:28 -07:00
Eddie Hung
80de03a7a6
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-26 11:24:39 -07:00
Eddie Hung
4d0014d1b1
Cleanup abc_box_id
2019-06-26 11:23:57 -07:00
Eddie Hung
612083a807
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-26 10:33:54 -07:00
Eddie Hung
5e1b8d458b
Remove unused var
2019-06-26 10:33:07 -07:00
Eddie Hung
988e6163ab
Add _nowide variants of LUT libraries in -nowidelut flows
2019-06-26 10:23:29 -07:00
Eddie Hung
741ebba70a
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
2019-06-26 10:10:16 -07:00
Eddie Hung
799b18263f
Merge branch 'koriakin/xc7nocarrymux' into xaig
2019-06-26 10:04:01 -07:00
Miodrag Milanovic
ea0b6258ab
Simulation model verilog fix
2019-06-26 18:34:34 +02:00
Eddie Hung
4ce329aefd
synth_ecp5 rename -nomux to -nowidelut, but preserve former
2019-06-26 09:33:48 -07:00
Eddie Hung
7389b043c0
Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into koriakin/xc7nocarrymux
2019-06-26 09:33:38 -07:00
Eddie Hung
177c26ca35
Rename -minmuxf to -widemux
2019-06-26 09:16:45 -07:00
Eddie Hung
184cfacfb5
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-26 09:15:28 -07:00
David Shah
0dd850e655
abc9: Add wire delays to synth_ice40
...
Signed-off-by: David Shah <dave@ds0.me>
2019-06-26 11:39:44 +01:00
whitequark
3d4102cfa4
Add more ECP5 Diamond flip-flops.
...
This includes all I/O registers, and a few more regular FFs where it
was convenient.
2019-06-26 01:57:29 +00:00
Eddie Hung
480a04cb3c
Realistic delays for RAM32X1D too
2019-06-25 09:34:28 -07:00
Eddie Hung
6095357390
Add RAM32X1D box info
2019-06-25 09:34:19 -07:00
Eddie Hung
6f36ec8ecf
Merge remote-tracking branch 'origin/master' into xaig
2019-06-25 09:33:11 -07:00
Eddie Hung
4238feed81
This optimisation doesn't seem to work...
2019-06-25 09:21:46 -07:00
Eddie Hung
158325956e
Realistic delays for RAM32X1D too
2019-06-24 23:05:28 -07:00
Eddie Hung
3825068a75
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-24 23:04:25 -07:00
Eddie Hung
2f770b7400
Use LUT delays for dist RAM delays
2019-06-24 23:02:53 -07:00
Eddie Hung
e1ba25d79f
Add RAM32X1D box info
2019-06-24 22:54:35 -07:00
Eddie Hung
1564eb8b54
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-24 22:48:49 -07:00
Eddie Hung
4fadb471a3
Re-enable dist RAM boxes for ECP5
2019-06-24 22:12:50 -07:00
Eddie Hung
a4a7e63d84
Revert "Re-enable dist RAM boxes for ECP5"
...
This reverts commit ca0225fcfa
.
2019-06-24 22:10:28 -07:00
Eddie Hung
ca0225fcfa
Re-enable dist RAM boxes for ECP5
2019-06-24 21:55:54 -07:00
Eddie Hung
152e682bd5
Add Xilinx dist RAM as comb boxes
2019-06-24 21:54:01 -07:00
Eddie Hung
f1675b88f6
Merge remote-tracking branch 'origin/eddie/ram32x1d' into xc7mux
2019-06-24 16:39:18 -07:00
Eddie Hung
efd04880db
Add RAM32X1D support
2019-06-24 16:16:50 -07:00
Eddie Hung
c3df895bf4
Reduce MuxFx resources in mux techmapping
2019-06-24 15:16:44 -07:00
Eddie Hung
db6a0b72b2
Reduce number of decomposed muxes during techmap
2019-06-24 14:28:56 -07:00
Eddie Hung
2e7992efff
Revert "Fix techmapping muxes some more"
...
This reverts commit 0aae3b4f43
.
2019-06-24 14:15:31 -07:00
Eddie Hung
7fbfcf20d1
Move comment
2019-06-24 14:15:00 -07:00
Eddie Hung
0aae3b4f43
Fix techmapping muxes some more
2019-06-24 12:50:48 -07:00
Eddie Hung
2b4501503d
Fix mux techmapping
2019-06-24 12:18:17 -07:00
Eddie Hung
aa1eeda567
Modify costs for muxcover
2019-06-24 11:51:55 -07:00
Eddie Hung
36e6da5396
Change synth_xilinx's -nomux to -minmuxf <int>
2019-06-24 10:04:01 -07:00
Eddie Hung
d54dceb547
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-22 19:44:17 -07:00
Eddie Hung
6027549464
Add comments to ecp5 box
2019-06-22 14:33:47 -07:00
Eddie Hung
792d0670c3
Add comment to xc7 box
2019-06-22 14:28:24 -07:00
Eddie Hung
63182ed57d
Fix and cleanup ice40 boxes for carry in/out
2019-06-22 14:27:41 -07:00
Eddie Hung
7903ebe3e0
Carry in/out box ordering now move to end, not swap with end
2019-06-22 14:18:42 -07:00
Eddie Hung
65c022c257
Remove DFF and RAMD box info for now
2019-06-21 20:41:14 -07:00
Eddie Hung
bbf3ad90f5
Remove $_MUX4_ techmap rule
2019-06-21 18:12:33 -07:00
Eddie Hung
39e0e006d5
Fix wreduce call (!!!), tweak muxcover costs
2019-06-21 18:12:07 -07:00
Eddie Hung
6c2cb51996
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-21 17:44:21 -07:00
Eddie Hung
1abe93e48d
Merge remote-tracking branch 'origin/master' into xaig
2019-06-21 17:43:29 -07:00
Eddie Hung
faa2d6fc1c
Constrain wreduce only if wide mux
2019-06-21 17:12:34 -07:00
Eddie Hung
aeee9dcad7
Simplify and comment out mux_map.v
2019-06-21 17:06:30 -07:00
Eddie Hung
ed00823b41
synth_xilinx to now wreduce except $mux, remove extra peepopt
2019-06-21 16:56:56 -07:00
Eddie Hung
29aee0989f
mux_map to no longer copy last value into 1'bx
2019-06-21 16:55:59 -07:00
Eddie Hung
8bce3fb329
Fix spacing
2019-06-21 16:55:34 -07:00
Eddie Hung
694d40719f
Fix spacing again, A_forward -> A_backward
2019-06-21 16:47:07 -07:00
Eddie Hung
11886c874c
Restore wreduce to synth_xilinx, after muxcover
2019-06-21 16:18:29 -07:00
Eddie Hung
44fc616fc7
Revert B_SIGNED optimisation, since only works for Y_WIDTH==1
2019-06-21 16:18:14 -07:00
Eddie Hung
4d6fac019a
Fix spacing
2019-06-21 16:06:13 -07:00
Eddie Hung
aa0b107afb
synth_xilinx to use _ABC macro, and perform muxpack again
2019-06-21 15:48:20 -07:00
Eddie Hung
9abde12110
Add $__XILINX_MUXF78 to preserve entire box
2019-06-21 15:47:42 -07:00
Eddie Hung
7acbea6b28
Fix alignment
2019-06-21 14:38:30 -07:00
Eddie Hung
f433a52374
Add FIXME about need for -mux4
2019-06-21 11:15:23 -07:00
Eddie Hung
c6b4653ebe
Since muxcover uses MUX4s, blast them back to gates here
2019-06-21 11:13:01 -07:00
Eddie Hung
dd22edcd28
Expand synth -coarse without wreduce, move muxcover
2019-06-21 11:12:32 -07:00
David Shah
a0d3d2bb41
ecp5: Improve mapping of $alu when BI is used
...
Signed-off-by: David Shah <dave@ds0.me>
2019-06-21 09:45:11 +01:00
Eddie Hung
e612dade12
Merge remote-tracking branch 'origin/master' into xaig
2019-06-20 19:00:36 -07:00
Eddie Hung
f11c9a419b
Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc
2019-06-20 17:38:16 -07:00
Eddie Hung
d1dadfcec8
Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc
2019-06-20 16:45:09 -07:00
Eddie Hung
9faab38e8d
mux_map to drop sign bit, and eliminate 'bx-es
2019-06-20 16:45:04 -07:00
Eddie Hung
f374e0ab7e
Merge remote-tracking branch 'origin/master' into xc7mux
2019-06-20 10:18:01 -07:00
acw1251
ce29ede801
Fixed small typo in ice40_unlut help summary
2019-06-19 16:39:46 -04:00
acw1251
0d888ee7ed
Fixed the help summary line for a few commands
2019-06-19 15:27:04 -04:00
Eddie Hung
4ca847a217
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-18 11:49:54 -07:00
Eddie Hung
8e0a47fb92
Really permute Xilinx LUT mappings as default LUT6.I5:A6
2019-06-18 11:48:48 -07:00
Eddie Hung
8f5e6d73ff
Revert "Fix (do not) permute LUT inputs, but permute mux selects"
...
This reverts commit da3d2eedd2
.
2019-06-18 11:35:21 -07:00
Eddie Hung
3d283e69f8
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-18 09:51:28 -07:00
Eddie Hung
b304744d15
Clean up
2019-06-18 09:50:37 -07:00
Eddie Hung
da3d2eedd2
Fix (do not) permute LUT inputs, but permute mux selects
2019-06-18 09:49:57 -07:00
Eddie Hung
2b0e28b261
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-17 22:29:34 -07:00
Eddie Hung
608a95eb01
Fix copy-pasta issue
2019-06-17 22:29:22 -07:00
Eddie Hung
59b4e69d16
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-17 22:25:14 -07:00
Eddie Hung
2a35c4ef94
Permute INIT for +/xilinx/lut_map.v
2019-06-17 22:24:35 -07:00
Eddie Hung
75f8b4cf10
Simplify comment
2019-06-17 19:14:41 -07:00
Eddie Hung
75d92fb590
Merge branch 'xaig' into xaig_dff
2019-06-17 19:11:07 -07:00
Eddie Hung
9d56c0d525
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-17 18:25:35 -07:00
Eddie Hung
840562943f
Update LUT7/8 delays to take account for [ABC]OUTMUX delay
2019-06-17 17:06:01 -07:00
Eddie Hung
8a86f9bb62
Add box delays for FD*
2019-06-17 15:13:05 -07:00
Eddie Hung
5ce672d1c5
Merge remote-tracking branch 'origin/xaig' into xaig_dff
2019-06-17 12:14:55 -07:00
Eddie Hung
c15ee827f4
Try -W 300
2019-06-17 10:29:06 -07:00
Eddie Hung
1ec450d6bf
Try -W 300
2019-06-16 12:08:03 -07:00
Eddie Hung
0c59bc0b75
Cleanup
2019-06-16 10:42:00 -07:00
Eddie Hung
d969a9060e
Add +/xilinx/abc_ff
2019-06-15 22:41:29 -07:00
Eddie Hung
9ec57b46c2
Fix spacing
2019-06-15 19:36:37 -07:00
Eddie Hung
c2f3f116d0
Use $__ABC_FF_ instead of $_FF_
2019-06-15 18:16:14 -07:00
Eddie Hung
65c7bafc64
Re-order alphabetically
2019-06-15 10:19:05 -07:00
Eddie Hung
a76c8a7ffd
Fix initialisation of flops
2019-06-15 09:46:35 -07:00
Eddie Hung
ac18a76beb
Map to $_FF_ instead of $_DFF_P_ to prevent recursion issues
2019-06-15 09:34:48 -07:00
Eddie Hung
295bb23ae0
Wrap FDRE with $__ABC_FDRE containing comb
2019-06-15 09:08:56 -07:00
Eddie Hung
842c110357
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-15 05:48:47 -07:00
Eddie Hung
bf312043d4
Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> O
2019-06-15 05:45:16 -07:00
Eddie Hung
b63b2a0bd4
Revert "Remove wide mux inference"
...
This reverts commit 738fdfe8f5
.
2019-06-14 12:50:24 -07:00
Eddie Hung
8fa74287a7
As per @daveshah1 remove async DFF timing from xilinx
2019-06-14 12:43:20 -07:00
Eddie Hung
97d2656375
Resolve comments from @daveshah1
2019-06-14 12:00:02 -07:00
Eddie Hung
2e34859a6b
Add XC7_WIRE_DELAY macro to synth_xilinx.cc
2019-06-14 11:38:22 -07:00
Eddie Hung
ba4b4a0088
Update delays based on SymbiFlow/prjxray-db
2019-06-14 11:33:10 -07:00
Eddie Hung
d47ff7ba87
Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}
2019-06-14 10:51:11 -07:00
Eddie Hung
94314ae2d5
Comment out dist RAM boxing on ECP5 for now
2019-06-14 10:42:30 -07:00
Eddie Hung
ee428f73ab
Remove WIP ABC9 flop support
2019-06-14 10:37:52 -07:00
Eddie Hung
627a62a797
Make doc consistent
2019-06-14 10:32:46 -07:00
David Shah
9566573054
ecp5: Add abc9 option
...
Signed-off-by: David Shah <dave@ds0.me>
2019-06-14 17:15:02 +01:00
Eddie Hung
75d89e56cf
Fix name clash
2019-06-13 14:27:07 -07:00
Eddie Hung
2052806d33
Fix LP SB_LUT4 timing
2019-06-13 08:24:33 -07:00
Eddie Hung
009255d11d
Move neg-pol to pos-pol mapping from ff_map to cells_map.v
2019-06-12 16:07:24 -07:00
Eddie Hung
c7f5091c2f
Reduce diff with master
2019-06-12 09:34:41 -07:00
Eddie Hung
f9433cc34b
Remove abc_flop{,_d} attributes from ice40/cells_sim.v
2019-06-12 09:29:30 -07:00
Eddie Hung
99267f660f
Fix spacing
2019-06-12 09:21:52 -07:00
Eddie Hung
738fdfe8f5
Remove wide mux inference
2019-06-12 09:20:46 -07:00
Eddie Hung
1e838a8913
Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"
2019-06-12 08:49:15 -07:00
Eddie Hung
4c9fde87d1
Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"
...
This reverts commit 2dffa4685b
.
2019-06-12 08:48:45 -07:00
Eddie Hung
2dffa4685b
Add "-W' wire delay arg to abc9, use from synth_xilinx
2019-06-11 17:10:47 -07:00
Eddie Hung
54379f9872
Disable dist RAM boxes due to comb loop
2019-06-11 12:02:51 -07:00
Eddie Hung
8a708d1fdb
Remove #ifndef ABC
2019-06-11 12:02:31 -07:00
Eddie Hung
b77c5da769
Revert "Revert "Move ff_map back after ABC for shregmap""
...
This reverts commit e473e74565
.
2019-06-10 14:37:09 -07:00
Eddie Hung
a1d4ae78a0
Revert "Rename shregmap -tech xilinx -> xilinx_dynamic"
...
This reverts commit 94a5f4e609
.
2019-06-10 14:34:43 -07:00
Eddie Hung
352c532bb2
Merge remote-tracking branch 'origin/master' into xc7mux
2019-06-10 11:02:54 -07:00
Simon Schubert
abf90b0403
ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k
2019-06-10 11:49:08 +02:00
Eddie Hung
816b5f5891
Comment out muxpack (currently broken)
2019-06-07 16:58:57 -07:00
Eddie Hung
88ae13e6a5
$__XILINX_MUX_ -> $__XILINX_SHIFTX
2019-06-06 15:32:36 -07:00
Eddie Hung
d3b7ae218b
Fix muxcover and its techmapping
2019-06-06 15:31:18 -07:00
Eddie Hung
a8c49168fb
Run muxpack and muxcover in synth_xilinx
2019-06-06 14:43:08 -07:00
Eddie Hung
7166dbe418
Remove abc_flop attributes for now
2019-06-06 14:35:38 -07:00
Eddie Hung
eaee250a6e
Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux
2019-06-06 14:06:59 -07:00
David Shah
30cedaca10
Merge pull request #1073 from whitequark/ecp5-diamond-iob
...
ECP5: implement most Diamond I/O buffer primitives
2019-06-06 11:22:49 +01:00
whitequark
f3a26730b6
ECP5: implement all Diamond I/O buffer primitives.
2019-06-06 10:18:33 +00:00
Eddie Hung
6ed15b7890
Update abc attributes on FD*E_1
2019-06-05 12:33:40 -07:00
Eddie Hung
67f744d428
Cleanup
2019-06-05 12:28:46 -07:00
Eddie Hung
2c18d530ea
Call shregmap -tech xilinx_static
2019-06-05 12:28:26 -07:00
Eddie Hung
e473e74565
Revert "Move ff_map back after ABC for shregmap"
...
This reverts commit 9b9bd4e19f
.
2019-06-05 11:53:06 -07:00
Eddie Hung
94a5f4e609
Rename shregmap -tech xilinx -> xilinx_dynamic
2019-06-04 14:34:36 -07:00
Eddie Hung
82d41bc2f2
Add space between -D and _ABC
2019-06-04 11:54:08 -07:00
Eddie Hung
f0e93f33cf
Add (* abc_flop_q *) to brams_bb.v
2019-06-04 11:53:51 -07:00
Eddie Hung
6cf092641f
Fix name clash
2019-06-04 09:56:36 -07:00
Eddie Hung
e260150321
Add mux_map.v for wide mux
2019-06-04 09:51:47 -07:00
Eddie Hung
9b9bd4e19f
Move ff_map back after ABC for shregmap
2019-06-03 23:43:23 -07:00
Eddie Hung
09b778744d
Respect -nocarry
2019-06-03 23:42:30 -07:00
Eddie Hung
5afa42432f
Fix pmux2shiftx logic
2019-06-03 23:29:45 -07:00
Eddie Hung
23a73ca624
Merge mistake
2019-06-03 23:19:22 -07:00
Eddie Hung
f81a0ed92e
Merge remote-tracking branch 'origin/master' into xc7mux
2019-06-03 23:07:08 -07:00
Eddie Hung
b6e59741ae
Typo
2019-06-03 20:21:41 -07:00
Eddie Hung
02973474df
Remove extra newline
2019-06-03 20:04:47 -07:00
Eddie Hung
c9a0bac541
IS_C_INVERTED
2019-06-03 19:45:56 -07:00
Eddie Hung
0ad50332d9
Execute techmap and arith_map simultaneously
2019-06-03 19:36:09 -07:00
Eddie Hung
ebcc85b9b8
Fix `ifndef
2019-06-03 12:37:02 -07:00
Eddie Hung
0092770317
Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now)
2019-06-03 12:34:55 -07:00
Eddie Hung
4da25c76b3
Ooopsie
2019-06-03 09:33:42 -07:00
Eddie Hung
9f44a71715
Consistent with xilinx
2019-06-03 09:23:43 -07:00
Eddie Hung
2228cef62f
Add flops as blackboxes
2019-05-31 18:11:46 -07:00
Eddie Hung
01f71085f2
Add FD*E_1 -> FD*E techmap rules
2019-05-31 18:11:24 -07:00
Eddie Hung
dea36d4366
Techmap flops before ABC again
2019-05-31 18:10:25 -07:00
Eddie Hung
eb08e71bd1
Merge branch 'xaig' into xc7mux
2019-05-31 13:03:03 -07:00
Eddie Hung
1ad33c3b5a
Remove whitebox attribute from DRAMs for now
2019-05-30 13:07:29 -07:00
Eddie Hung
fdfc18be91
Carry in/out to be the last input/output for chains to be preserved
2019-05-30 01:23:36 -07:00
Eddie Hung
276f5f8b81
Some more realistic delays...
2019-05-29 22:55:34 -07:00
Eddie Hung
f228621b80
Typo
2019-05-28 09:36:01 -07:00
Eddie Hung
e032e5bcde
Make MUXF{7,8} and CARRY4 whitebox
2019-05-27 23:09:06 -07:00
Eddie Hung
54e28eb3ea
Re-enable lib_whitebox
2019-05-27 23:08:55 -07:00
Eddie Hung
4311b9b583
Blackboxes
2019-05-26 11:32:02 -07:00
Eddie Hung
66701c5fcc
Muck about with LUT delays some more
2019-05-26 02:52:48 -07:00
Eddie Hung
ca5774ed40
Try new LUT delays
2019-05-24 20:39:55 -07:00
Eddie Hung
60af2ca94d
Transpose CARRY4 delays
2019-05-24 14:09:15 -07:00
Eddie Hung
52e9036d39
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-23 13:38:04 -07:00
Eddie Hung
68359bcd6f
Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux
2019-05-23 13:37:53 -07:00
Eddie Hung
99a3fee8f4
Add "min bits" and "min wports" to xilinx dram rules
2019-05-23 11:32:28 -07:00
Eddie Hung
ae89e6ab26
Add whitebox support to DRAM
2019-05-23 08:58:57 -07:00
Eddie Hung
4f44e3399b
shift register inference before mux
2019-05-22 02:36:28 -07:00
Eddie Hung
9b1078b9bd
Fix/workaround symptom unveiled by #1023
2019-05-21 18:50:02 -07:00
Eddie Hung
ee8435b820
Instead of MUXCY/XORCY use CARRY4 (with timing)
2019-05-21 16:19:45 -07:00
Eddie Hung
36a219063a
Modify LUT area cost to be same as old abc
2019-05-21 14:31:19 -07:00
Eddie Hung
fb09c6219b
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-21 14:21:00 -07:00
Clifford Wolf
c4b8575f43
Add "wreduce -keepdc", fixes #1016
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-20 15:36:13 +02:00
Sylvain Munaut
4f9183d107
ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-05-13 12:51:06 +02:00
Clifford Wolf
04ef222cfb
Add "stat -tech xilinx"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-11 09:24:52 +02:00
Ben Widawsky
05d8cc4567
Fix formatting for synth_intel.cc
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This is realized through the recently added .clang-format file.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-05-09 08:40:05 -07:00
Clifford Wolf
09467bb9a3
Add "synth_xilinx -arch"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-07 15:04:36 +02:00
Eddie Hung
d9c4644e88
Merge remote-tracking branch 'origin/master' into clifford/specify
2019-05-03 15:05:57 -07:00
Eddie Hung
c2e29ab809
Rename cells_map.v to prevent clash with ff_map.v
2019-05-03 14:40:32 -07:00
Clifford Wolf
373b236108
Merge pull request #969 from YosysHQ/clifford/pmgenstuff
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Improve pmgen, Add "peepopt" pass with shift-mul pattern
2019-05-03 20:39:50 +02:00
Eddie Hung
283e33ba5a
Trim off leading 1'bx in A
2019-05-02 16:02:37 -07:00
Eddie Hung
fc72f07efd
Add don't care optimisation
2019-05-02 15:01:37 -07:00
Eddie Hung
d80445e049
Use new peepopt from #969
2019-05-02 11:35:57 -07:00
Eddie Hung
8829cba901
Merge remote-tracking branch 'origin/clifford/pmgenstuff' into xc7mux
2019-05-02 11:25:34 -07:00
Eddie Hung
95867109ea
Revert to pre-muxcover approach
2019-05-02 11:25:10 -07:00
Eddie Hung
d05ac7257e
Missing help_mode
2019-05-02 11:14:28 -07:00
Eddie Hung
3b5e8c86a4
Fix -nocarry
2019-05-02 11:00:49 -07:00
Eddie Hung
5cd19b52da
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-02 10:44:59 -07:00
Eddie Hung
d394b9301b
Back to passing all xc7srl tests!
2019-05-01 18:23:21 -07:00
Eddie Hung
31ff0d8ef5
Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine
2019-05-01 18:09:38 -07:00
Clifford Wolf
a27eeff573
Merge pull request #966 from YosysHQ/clifford/fix956
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Drive dangling wires with init attr with their init value
2019-04-30 18:08:41 +02:00
Clifford Wolf
9d117eba9d
Add handling of init attributes in "opt_expr -undriven"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 14:46:12 +02:00
Marcin Kościelnicki
98e5a625c4
synth_xilinx: Add -nocarry and -nomux options.
2019-04-30 12:54:21 +02:00
Clifford Wolf
d2d402e625
Run "peepopt" in generic "synth" pass and "synth_ice40"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 08:10:37 +02:00
Eddie Hung
e97178a888
WIP
2019-04-28 12:51:00 -07:00
Eddie Hung
af840bbc63
Move neg-pol to pos-pol mapping from ff_map to cells_map.v
2019-04-28 12:36:04 -07:00
Eddie Hung
4aca928033
Fix spacing
2019-04-26 19:46:34 -07:00
Eddie Hung
d855683917
Revert synth_xilinx 'fine' label more to how it used to be...
2019-04-26 16:53:16 -07:00
Eddie Hung
ccc283737d
Apparently, this reduces number of MUXCY/XORCY
2019-04-26 16:28:48 -07:00
Eddie Hung
e31e21766d
Try a different approach with 'muxcover'
2019-04-26 16:09:54 -07:00
Eddie Hung
76b7c5d4cc
Merge remote-tracking branch 'origin/master' into xc7mux
2019-04-26 15:35:55 -07:00
Eddie Hung
ea0e0722bb
Where did this check come from!?!
2019-04-26 15:35:34 -07:00
Eddie Hung
6b9ca7cd6d
Remove split_shiftx call
2019-04-26 15:32:58 -07:00
Eddie Hung
8469d9fe9f
Missing newline
2019-04-26 14:51:37 -07:00
Eddie Hung
727eec04c5
Refactor synth_xilinx to auto-generate doc
2019-04-26 14:32:18 -07:00
Eddie Hung
1ea6d7920f
Cleanup ice40
2019-04-26 14:31:59 -07:00
Eddie Hung
f14d7f0df6
Cleanup superseded
2019-04-25 19:43:41 -07:00
Eddie Hung
019c48b508
bitblast_shiftx -> split_shiftx
2019-04-25 19:38:35 -07:00
Eddie Hung
feff976454
synth_xilinx to call bitblast_shiftx
2019-04-25 17:11:18 -07:00
Eddie Hung
f96d82a5f1
Add -nocarry option to synth_xilinx
2019-04-24 16:46:41 -07:00
Clifford Wolf
64925b4e8f
Improve $specrule interface
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 22:57:10 +02:00
Eddie Hung
91c3afcab7
Use nonblocking
2019-04-23 13:42:06 -07:00
Clifford Wolf
4575e4ad86
Improve $specrule interface
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 22:18:04 +02:00
Clifford Wolf
71c38d9de5
Add $specrule cells for $setup/$hold/$skew specify rules
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
e807e88b60
Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
a7e11261bd
Add $specify2 and $specify3 cells to simlib
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Eddie Hung
0bd2bfa737
Merge remote-tracking branch 'origin/master' into xaig
2019-04-22 18:15:28 -07:00
Eddie Hung
60026842b2
Tweak
2019-04-22 17:59:56 -07:00
Eddie Hung
26e461f47d
Fix for A_WIDTH == 2 but B_WIDTH==3
2019-04-22 17:58:28 -07:00
Eddie Hung
1fa2c36fbd
Trim A_WIDTH by Y_WIDTH-1
2019-04-22 17:14:11 -07:00
Eddie Hung
69863f7698
Add comment
2019-04-22 16:58:44 -07:00
Eddie Hung
61161faefc
Fix for mux_case_* mappings
2019-04-22 16:56:18 -07:00
Eddie Hung
ac1e13819e
Fix for non-pow2 width muxes
2019-04-22 14:26:13 -07:00
Eddie Hung
75b96b1aff
Add synth_xilinx -nomux option
2019-04-22 12:36:15 -07:00
Eddie Hung
79fb291dbe
Cleanup, call pmux2shiftx even without -nosrl
2019-04-22 12:14:37 -07:00
Eddie Hung
4cfef7897f
Merge branch 'xaig' into xc7mux
2019-04-22 11:58:59 -07:00
Eddie Hung
4486a98fd5
Merge remote-tracking branch 'origin/xc7srl' into xc7mux
2019-04-22 11:45:49 -07:00
Eddie Hung
ec88129a5c
Update help message
2019-04-22 11:38:23 -07:00
Eddie Hung
4883391b63
Merge remote-tracking branch 'origin/master' into xaig
2019-04-22 11:19:52 -07:00
Eddie Hung
0e76718720
Move 'shregmap -tech xilinx' into map_cells
2019-04-22 10:45:39 -07:00
Eddie Hung
e300b1922c
Merge remote-tracking branch 'origin/master' into xc7srl
2019-04-22 10:36:27 -07:00
Clifford Wolf
0e7901e45c
Merge pull request #941 from Wren6991/sim_lib_io_clke
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ice40 cells_sim.v: update clock enable behaviour based on hardware experiments
2019-04-22 09:11:13 +02:00
Clifford Wolf
913659d644
Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master
2019-04-22 09:09:27 +02:00
Clifford Wolf
cf1ba46fa0
Re-added clean after techmap in synth_xilinx
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 09:03:11 +02:00
Clifford Wolf
cbd9b8a3f3
Merge pull request #916 from YosysHQ/map_cells_before_map_luts
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synth_xilinx to map_cells before map_luts
2019-04-22 09:01:00 +02:00
Clifford Wolf
19fd411e77
Merge pull request #911 from mmicko/gowin-nobram
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Make nobram false by default for gowin
2019-04-22 08:58:09 +02:00
Eddie Hung
d342b5b135
Tidy up, fix for -nosrl
2019-04-21 15:33:03 -07:00
Eddie Hung
d7f0700bae
Convert to use #945
2019-04-21 15:19:02 -07:00
Eddie Hung
726e2da8f2
Merge branch 'map_cells_before_map_luts' into xc7srl
2019-04-21 14:28:55 -07:00
Eddie Hung
a3371e118b
Merge branch 'master' into map_cells_before_map_luts
2019-04-21 14:24:50 -07:00
Eddie Hung
ae95aba60a
Add comments
2019-04-21 14:16:59 -07:00
Eddie Hung
d99422411f
Use new pmux2shiftx from #944 , remove my old attempt
2019-04-21 14:16:34 -07:00
Luke Wren
71da836300
ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware experiments
2019-04-21 21:40:11 +01:00
Eddie Hung
caec7f9d2c
Merge remote-tracking branch 'origin/master' into xaig
2019-04-20 12:23:49 -07:00
Eddie Hung
13ad19482f
Merge remote-tracking branch 'origin' into xc7srl
2019-04-20 10:41:43 -07:00
Eddie Hung
af4652522f
ABC_FLOPS -> ABC_MODEL -- only whitebox if ABC_MODEL set
2019-04-19 21:09:55 -07:00
Eddie Hung
2776925bcf
Make SB_DFF whitebox
2019-04-19 08:36:38 -07:00
Eddie Hung
19b660ff6e
Fix SB_DFF comb model
2019-04-18 23:07:16 -07:00
Eddie Hung
0919f36b88
Missing close bracket
2019-04-18 17:50:11 -07:00
Eddie Hung
cf66416110
Annotate SB_DFF* with abc_flop and abc_box_id
2019-04-18 17:46:53 -07:00
Eddie Hung
ca1eb98a97
Add SB_DFF* to boxes
2019-04-18 17:46:32 -07:00
Eddie Hung
4c327cf316
Use new -wb flag for ABC flow
2019-04-18 10:32:41 -07:00
Eddie Hung
9278192efe
Also update Makefile.inc
2019-04-18 09:58:34 -07:00
Eddie Hung
7b6ab937c1
Make SB_LUT4 a blackbox
2019-04-18 09:05:22 -07:00
Eddie Hung
8024f41897
Fix rename
2019-04-18 09:04:34 -07:00
Eddie Hung
ed5e75ed7d
Rename to abc_*.{box,lut}
2019-04-18 09:02:58 -07:00
Eddie Hung
6008bb7002
Revert "synth_* with -retime option now calls abc with -D 1 as well"
...
This reverts commit 9a6da9a79a
.
2019-04-18 07:59:16 -07:00
Eddie Hung
0642baabbc
Merge branch 'master' into eddie/fix_retime
2019-04-18 07:57:17 -07:00
Eddie Hung
8fd455c910
Update Makefile.inc too
2019-04-17 15:19:48 -07:00
Eddie Hung
c795e14d25
Reduce to three devices: hx, lp, u
2019-04-17 15:19:02 -07:00
Eddie Hung
5c0853fc51
Add up5k timings
2019-04-17 15:10:39 -07:00
Eddie Hung
4b520ae627
Fix grammar
2019-04-17 15:10:22 -07:00
Eddie Hung
3105a8a653
Update error message
2019-04-17 15:07:44 -07:00
Eddie Hung
6f3e5297db
Add "-device" argument to synth_ice40
2019-04-17 15:04:46 -07:00
Eddie Hung
671cca59a9
Missing abc_flop_q attribute on SPRAM
2019-04-17 14:44:08 -07:00
Eddie Hung
437fec0d88
Map to SB_LUT4 from fastest input first
2019-04-17 13:01:17 -07:00
Eddie Hung
58847df1b9
Mark seq output ports with "abc_flop_q" attr
2019-04-17 12:27:45 -07:00
Eddie Hung
1eade06671
Also update Makefile.inc
2019-04-17 12:27:02 -07:00
Eddie Hung
4fb9ccfcd8
synth_ice40 to use renamed files
2019-04-17 12:22:03 -07:00
Eddie Hung
42c33db22c
Rename to abc.*
2019-04-17 12:15:34 -07:00
Eddie Hung
c1ebe51a75
Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues"
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This reverts commit a7632ab332
.
2019-04-17 11:10:20 -07:00
Eddie Hung
a7632ab332
Try using an ICE40_CARRY_LUT primitive to avoid ABC issues
2019-04-17 11:10:04 -07:00
Eddie Hung
17fb6c3522
Fix spacing
2019-04-17 08:40:50 -07:00
Eddie Hung
743c164eee
Add SB_LUT4 to box library
2019-04-16 17:34:11 -07:00
Eddie Hung
7980118d74
Add ice40 box files
2019-04-16 16:39:30 -07:00
Eddie Hung
cbb85e40e8
Add MUXCY and XORCY to cells_box.v
2019-04-16 14:53:28 -07:00
Eddie Hung
aece97024d
Fix spacing
2019-04-16 13:16:20 -07:00
Eddie Hung
53b19ab1f5
Make cells.box whiteboxes not blackboxes
2019-04-16 12:43:14 -07:00
Eddie Hung
5189695362
read_verilog cells_box.v before techmap
2019-04-16 12:41:56 -07:00
Eddie Hung
d259e6dc14
synth_xilinx: before abc read +/xilinx/cells_box.v
2019-04-16 11:21:46 -07:00
Eddie Hung
3ac4977b70
Add +/xilinx/cells_box.v containing models for ABC boxes
2019-04-16 11:21:03 -07:00
Eddie Hung
8c6cf07acf
Revert "Add abc_box_id attribute to MUXF7/F8 cells"
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This reverts commit 8fbbd9b129
.
2019-04-16 11:14:59 -07:00
Eddie Hung
8fbbd9b129
Add abc_box_id attribute to MUXF7/F8 cells
2019-04-15 22:25:09 -07:00
Eddie Hung
538592067e
Merge branch 'xaig' into xc7mux
2019-04-15 22:04:20 -07:00
Diego
f9272fc56d
GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow
2019-04-12 23:40:02 -05:00
Eddie Hung
04e466d5e4
Add support for synth_xilinx -abc9 and ignore abc9 -dress opt
2019-04-12 12:28:37 -07:00
Eddie Hung
f77da46a87
Merge remote-tracking branch 'origin/master' into xaig
2019-04-12 12:21:48 -07:00
Eddie Hung
db1a5ec6a2
Merge pull request #928 from litghost/add_xc7_sim_models
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Add additional cells sim models for core 7-series primitives.
2019-04-12 11:52:45 -07:00
Eddie Hung
8228b593ef
Merge remote-tracking branch 'origin/master' into xc7mux
2019-04-12 09:46:07 -07:00
Keith Rothman
1f9235ede5
Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-04-12 09:35:15 -07:00
Diego
643ae9bfc5
Fixing issues in CycloneV cell sim
2019-04-11 19:59:03 -05:00
Eddie Hung
233edf00fe
Fix cells_map.v some more
2019-04-11 10:48:14 -07:00
Eddie Hung
8658b56a08
More fine tuning
2019-04-11 10:08:05 -07:00
Eddie Hung
0ec8564099
Fix cells_map.v
2019-04-11 10:04:58 -07:00
Eddie Hung
bca3779657
Fix typo
2019-04-11 09:25:19 -07:00
Eddie Hung
87b8d29a90
Juggle opt calls in synth_xilinx
2019-04-11 09:13:39 -07:00
Eddie Hung
cd7b2de27f
WIP for cells_map.v -- maybe working?
2019-04-10 18:05:09 -07:00
Eddie Hung
3d577586fd
Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1
2019-04-10 16:15:23 -07:00
Eddie Hung
3f5dab0d09
Fix for when B_SIGNED = 1
2019-04-10 14:51:10 -07:00
Eddie Hung
32561332b2
Update doc for synth_xilinx
2019-04-10 14:48:58 -07:00
Eddie Hung
17a02df05c
ff_map.v after abc
2019-04-10 12:36:06 -07:00
Eddie Hung
1ec949d5ed
Tidy up
2019-04-10 09:02:42 -07:00
Eddie Hung
526aef9c2a
Move map_cells to before map_luts
2019-04-10 08:50:31 -07:00
Eddie Hung
e0b46eb4cb
WIP for $shiftx to wide mux
2019-04-10 08:49:55 -07:00
Eddie Hung
4dac9818bd
Update LUT delays
2019-04-10 08:49:39 -07:00
Eddie Hung
9a6da9a79a
synth_* with -retime option now calls abc with -D 1 as well
2019-04-10 08:32:53 -07:00
Eddie Hung
3e368593eb
Add cells.lut to techlibs/xilinx/
2019-04-09 14:33:37 -07:00
Eddie Hung
fd88ab5c83
synth_xilinx to call abc with -lut +/xilinx/cells.lut
2019-04-09 14:32:39 -07:00
Eddie Hung
b9e19071b8
Add delays to cells.box
2019-04-09 14:32:10 -07:00
Keith Rothman
e107ccdde8
Fix LUT6_2 definition.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-04-09 11:43:19 -07:00
Eddie Hung
f2042fc7c4
synth_xilinx with abc9 to use -box
2019-04-09 11:01:46 -07:00
Eddie Hung
2ae26b986c
Add techlibs/xilinx/cells.box
2019-04-09 10:58:58 -07:00
Eddie Hung
3fc474aa73
Add support for synth_xilinx -abc9 and ignore abc9 -dress opt
2019-04-09 10:06:44 -07:00
Keith Rothman
5e0339855f
Add additional cells sim models for core 7-series primatives.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-04-09 09:01:53 -07:00
Eddie Hung
bca3cf6843
Merge branch 'master' into xaig
2019-04-08 16:31:59 -07:00
Eddie Hung
1d526b7f06
Call shregmap twice -- once for variable, another for fixed
2019-04-05 17:35:49 -07:00
Eddie Hung
a5f33b5409
Move dffinit til after abc
2019-04-05 16:20:43 -07:00
Eddie Hung
0364a5d811
Merge branch 'eddie/fix_retime' into xc7srl
2019-04-05 15:46:18 -07:00
Eddie Hung
9758701574
Move techamp t:$_DFF_?N? to before abc call
2019-04-05 15:39:05 -07:00
Eddie Hung
23a6533e98
Retry
2019-04-05 15:31:54 -07:00
Eddie Hung
8b6085254a
Resolve @daveshah1 comment, update synth_xilinx help
2019-04-05 15:15:13 -07:00
Eddie Hung
ff0912c75e
synth_xilinx to techmap FFs after abc call, otherwise -retime fails
2019-04-05 14:43:06 -07:00
Eddie Hung
544843da71
techmap inside map_cells stage
2019-04-05 12:55:52 -07:00
Eddie Hung
7b7ddbdba7
Merge branch 'map_cells_before_map_luts' into xc7srl
2019-04-04 08:13:34 -07:00
Eddie Hung
e3f20b17af
Missing techmap entry in help
2019-04-04 08:13:10 -07:00
Eddie Hung
2fb02247a7
Use soft-logic, not LUT3 instantiation
2019-04-04 08:10:40 -07:00
Eddie Hung
572603409c
Merge branch 'map_cells_before_map_luts' into xc7srl
2019-04-04 07:54:42 -07:00
Eddie Hung
d9cb787391
synth_xilinx to map_cells before map_luts
2019-04-04 07:48:13 -07:00
Eddie Hung
77755b5a66
Cleanup comments
2019-04-04 07:41:40 -07:00
Eddie Hung
736e19f02d
t:$dff* -> t:$dff t:$dffe
2019-04-04 07:39:19 -07:00
Eddie Hung
0e2d929cea
-nosrl meant when -nobram
2019-04-03 08:28:07 -07:00
Eddie Hung
ff385a5ad0
Remove duplicate STARTUPE2
2019-04-03 08:14:09 -07:00
Eddie Hung
88630cd02c
Disable shregmap in synth_xilinx if -retime
2019-04-03 07:14:20 -07:00
Miodrag Milanovic
df92e9bdc2
Make nobram false by default for gowin
2019-04-02 19:21:01 +02:00
Eddie Hung
f9fb05cf66
synth_xilinx to use shregmap with -minlen 3
2019-03-25 13:18:55 -07:00
Eddie Hung
46753cf89f
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-22 13:10:42 -07:00
David Shah
46f6a60d58
xilinx: Add keep attribute where appropriate
...
Signed-off-by: David Shah <dave@ds0.me>
2019-03-22 13:57:17 +00:00
Eddie Hung
4cc6b3e942
Add '-nosrl' option to synth_xilinx
2019-03-21 15:04:44 -07:00
Eddie Hung
81c207fb9b
Fine tune cells_map.v
2019-03-20 10:55:14 -07:00
Eddie Hung
505e4c2d59
Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length
2019-03-19 21:58:05 -07:00
Eddie Hung
5445cd4d00
Add support for variable length Xilinx SRL > 128
2019-03-19 17:44:33 -07:00
Eddie Hung
ae2a625d05
Restore original synth_xilinx commands
2019-03-19 16:14:08 -07:00
Eddie Hung
9156e18f92
Fix spacing
2019-03-19 16:12:32 -07:00
Eddie Hung
f239cb821e
Fix INIT for variable length SRs that have been bumped up one
2019-03-19 14:54:43 -07:00
Eddie Hung
24553326dd
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-19 13:11:30 -07:00
Clifford Wolf
fe1fb1336b
Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-19 20:30:28 +01:00
Eddie Hung
fadeadb8c8
Only accept <128 for variable length, only if $shiftx exclusive
2019-03-16 08:51:13 -07:00
Eddie Hung
29a8d4745e
Cleanup synth_xilinx
2019-03-15 23:01:40 -07:00
Eddie Hung
06f8f2654a
Working
2019-03-15 19:13:40 -07:00
Eddie Hung
e7ef7fa443
Reverse bits in INIT parameter for Xilinx, since MSB is shifted first
2019-03-14 09:38:42 -07:00
Eddie Hung
af5706c2a3
Misspell
2019-03-14 09:06:56 -07:00
Eddie Hung
8af9979aab
Revert "Add shregmap -init_msb_first and use in synth_xilinx"
...
This reverts commit 26ecbc1aee
.
2019-03-14 09:01:48 -07:00
Eddie Hung
f1a8e8a480
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-14 08:59:19 -07:00
Eddie Hung
26ecbc1aee
Add shregmap -init_msb_first and use in synth_xilinx
2019-03-14 08:10:02 -07:00
Eddie Hung
79b4a275ce
Fix cells_map for SRL
2019-03-14 08:09:48 -07:00
Eddie Hung
edca2f1163
Move shregmap until after first techmap
2019-03-13 17:13:52 -07:00
Eddie Hung
24f129ddfb
Refactor $__SHREG__ in cells_map.v
2019-03-13 16:17:54 -07:00
Clifford Wolf
9284cf92b8
Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-12 20:14:18 +01:00
Clifford Wolf
ff4c2a14ae
Fix typo in ice40_braminit help msg
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-09 13:24:55 -08:00
Clifford Wolf
2ace1b0041
Merge pull request #859 from smunaut/ice40_braminit
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iCE40 BRAM primitives init from file
2019-03-09 13:24:10 -08:00
Sylvain Munaut
5b6f591033
ice40: Run ice40_braminit pass by default
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-03-08 00:15:46 +01:00
Sylvain Munaut
e71055cfe8
ice40: Add ice40_braminit pass to allow initialization of BRAM from file
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This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will
initialize content from a hex file. Same behavior is imlemented in the
simulation model and in a new pass for actual synthesis
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-03-08 00:15:46 +01:00
Clifford Wolf
350dfd3745
Add link to SF2 / igloo2 macro library guide
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-07 09:08:26 -08:00
Clifford Wolf
8b0719d1e3
Improvements in sf2 cells_sim.v
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-06 16:18:49 -08:00
Clifford Wolf
2d2c1617ee
Add sf2 techmap rules for more FF types
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-06 15:47:54 -08:00
Clifford Wolf
78762316aa
Refactor SF2 iobuf insertion, Add clkint insertion
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-06 00:41:02 -08:00
Clifford Wolf
da5181a3df
Improvements in SF2 flow and demo
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-05 20:36:00 -08:00
Clifford Wolf
bfcd46dbd3
Merge pull request #842 from litghost/merge_upstream
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Changes required for VPR place and route in synth_xilinx
2019-03-05 15:33:19 -08:00
Clifford Wolf
724576a4e2
Merge pull request #850 from daveshah1/ecp5_warn_conflict
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ecp5: Demote conflicting FF init values to a warning
2019-03-05 15:23:01 -08:00
Clifford Wolf
13844c7658
Use "write_edif -pvector bra" for Xilinx EDIF files
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-05 15:16:13 -08:00
Keith Rothman
228f132ec3
Revert BRAM WRITE_MODE changes.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-04 09:22:22 -08:00
David Shah
777864d02e
ecp5: Demote conflicting FF init values to a warning
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Signed-off-by: David Shah <dave@ds0.me>
2019-03-04 11:26:20 +00:00
Keith Rothman
3e16f75bc6
Revert FF models to include IS_x_INVERTED parameters.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 14:41:21 -08:00
Keith Rothman
5ebeca12eb
Use singular for disabling of DRAM or BRAM inference.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 14:35:14 -08:00
Keith Rothman
eccaf101d8
Modify arguments to match existing style.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 12:14:27 -08:00
Keith Rothman
3090951d54
Changes required for VPR place and route synth_xilinx.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 12:02:27 -08:00
Miodrag Milanovic
ca2b3feed8
Fix ECP5 cells_sim for iverilog
2019-03-01 19:25:23 +01:00
Clifford Wolf
a82a7eb42e
Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
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ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
2019-02-28 20:27:27 -08:00
Elms
cd2902ab1f
ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
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EBLIF output .param will only use necessary 2 bits
Signed-off-by: Elms <elms@freshred.net>
2019-02-28 16:23:40 -08:00
Larry Doolittle
e2fc18f27b
Reduce amount of trailing whitespace in code base
2019-02-28 14:58:11 -08:00
Clifford Wolf
41e5028f98
Merge pull request #794 from daveshah1/ecp5improve
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ECP5 Improvements
2019-02-28 14:46:56 -08:00
Eddie Hung
1da0909662
Remove SRL16/32 from cells_xtra
2019-02-28 13:56:45 -08:00
Eddie Hung
73ddab6960
Add SRL16 and SRL32 sim models
2019-02-28 13:56:22 -08:00
Eddie Hung
8aab7fe7e6
Fix SRL16/32 techmap off-by-one
2019-02-28 13:56:00 -08:00
Eddie Hung
fe4d6898de
synth_xilinx to call shregmap with enable support
2019-02-28 11:17:13 -08:00
Eddie Hung
68f38f2ee0
synth_xilinx to use shregmap with -params too
2019-02-28 10:21:05 -08:00
Eddie Hung
c9ab18889a
synth_xilinx to now have shregmap call after dff2dffe
2019-02-28 09:32:29 -08:00
Eddie Hung
c29f0c5048
Add techmap rule for $__SHREG_DFF_P_ to SRL16/32
2019-02-28 09:31:24 -08:00
Eddie Hung
f7c7003a19
Merge remote-tracking branch 'origin/master' into xaig
2019-02-26 13:16:03 -08:00
Larry Doolittle
7a40294e93
techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module
2019-02-26 09:40:46 -08:00
Larry Doolittle
61fc411c5d
Clean up some whitepsace outliers
2019-02-26 09:39:46 -08:00
David Shah
fa2f595cfa
ecp5: Compatibility with Migen AsyncResetSynchronizer
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-25 13:24:30 +00:00
Clifford Wolf
344afdcd5f
Merge pull request #740 from daveshah1/improve_dress
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Improve ABC netname preservation
2019-02-22 01:16:34 +01:00
Eddie Hung
a8803a1519
Merge remote-tracking branch 'origin/master' into xaig
2019-02-21 11:23:00 -08:00
Clifford Wolf
2fe1c830eb
Bugfix in ice40_dsp
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 13:28:46 +01:00
Eddie Hung
45ddd9066e
synth to take -abc9 argument
2019-02-20 11:08:49 -08:00
Clifford Wolf
84999a7e68
Add ice40 test_dsp_map test case generator
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 17:18:59 +01:00
Clifford Wolf
218e9051bb
Add "synth_ice40 -dsp"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 16:42:27 +01:00
Clifford Wolf
7bf4e4a185
Improve iCE40 SB_MAC16 model
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 12:55:20 +01:00
Eddie Hung
f9af902532
Merge branch 'master' into xaig
2019-02-19 14:20:04 -08:00
David Shah
bb56cb738d
ecp5: Add DDRDLLA
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-19 19:34:37 +00:00
David Shah
c36f15b489
ecp5: Add DELAYF/DELAYG blackboxes
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-19 14:10:43 +00:00
Clifford Wolf
62493c91b2
Add first draft of functional SB_MAC16 model
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-19 14:47:27 +01:00
Eddie Hung
323dd0e608
synth_ice40 to have new -abc9 arg
2019-02-14 13:19:27 -08:00
David Shah
e0bc190879
ecp5: Add ECLKSYNCB blackbox
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Signed-off-by: David Shah <dave@ds0.me>
2019-02-13 11:23:25 +00:00
David Shah
7913baedd8
ecp5: Full set of IO-related blackboxes
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Signed-off-by: David Shah <dave@ds0.me>
2019-02-12 12:04:41 +00:00
Eddie Hung
e8f4dc739c
Cope WIDTH of ff/latch cells is default of zero
2019-02-06 15:51:12 -08:00
Eddie Hung
742b4e01b4
Add INIT parameter to all ff/latch cells
2019-02-06 14:16:26 -08:00
David Shah
95789c6136
ecp5: Use abc -dress
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-06 22:23:13 +01:00
David Shah
7ef2333497
ice40: Use abc -dress in synth_ice40
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-06 22:23:13 +01:00
Miodrag Milanovic
0de328da8f
Fixed Anlogic simulation model
2019-01-25 19:25:25 +01:00
David Shah
549b8e74b2
ecp5: Support for flipflop initialisation
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Signed-off-by: David Shah <dave@ds0.me>
2019-01-22 16:02:56 +00:00
David Shah
ee8c9e854f
ecp5: Add LSRMODE to flipflops for PRLD support
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Signed-off-by: David Shah <dave@ds0.me>
2019-01-21 12:35:22 +00:00
David Shah
d8003e87d1
ecp5: More blackboxes
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Signed-off-by: David Shah <dave@ds0.me>
2019-01-21 12:34:34 +00:00
David Shah
01ea72f53a
ecp5: Increase threshold for ALU mapping
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Signed-off-by: David Shah <dave@ds0.me>
2019-01-21 12:33:47 +00:00
Clifford Wolf
db5765b443
Add SF2 IO buffer insertion
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-17 14:38:37 +01:00
Clifford Wolf
841ca74c90
Add "synth_sf2 -vlog", fix "synth_sf2 -edif"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-17 13:33:45 +01:00
Clifford Wolf
e041ae3c6d
Merge pull request #777 from mmicko/achronix_cell_sim_fix
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Fix cells_sim.v for Achronix FPGA
2019-01-04 15:18:18 +01:00
Miodrag Milanovic
50ef4561d4
Fix cells_sim.v for Achronix FPGA
2019-01-04 15:15:23 +01:00
Miodrag Milanovic
3b17c9018a
Unify usage of noflatten among architectures
2019-01-04 11:37:25 +01:00
Clifford Wolf
56ca1e6afc
Merge pull request #755 from Icenowy/anlogic-dram-init
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anlogic: implement DRAM initialization
2019-01-02 16:28:18 +01:00
Clifford Wolf
979de95cf6
Merge pull request #750 from Icenowy/anlogic-ff-init
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Initialization of Anlogic DFFs
2019-01-02 15:52:22 +01:00
Clifford Wolf
da1c8d8d3d
Merge pull request #772 from whitequark/synth_lut
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synth: add k-LUT mode
2019-01-02 15:44:57 +01:00
Clifford Wolf
00330c741a
Merge pull request #771 from whitequark/techmap_cmp2lut
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cmp2lut: new techmap pass
2019-01-02 15:43:10 +01:00
whitequark
efa278e232
Fix typographical and grammatical errors and inconsistencies.
...
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
whitequark
17b2831356
synth_ice40: use 4-LUT coarse synthesis mode.
2019-01-02 08:25:55 +00:00
whitequark
18174202a9
synth: add k-LUT mode.
2019-01-02 08:25:03 +00:00
whitequark
fdff32dd73
synth: improve script documentation. NFC.
2019-01-02 08:05:44 +00:00
whitequark
a91892bba4
cmp2lut: new techmap pass.
2019-01-02 07:53:31 +00:00
Clifford Wolf
e09e49ca54
Merge pull request #766 from Icenowy/anlogic-latches
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anlogic: add latch cells
2018-12-31 15:52:01 +01:00
Larry Doolittle
ebe9351f82
Fix 7 instances of add_share_file to add_gen_share_file
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in techlibs/ecp5/Makefile.inc to permit out-of-tree builds
2018-12-29 12:53:12 +01:00
Icenowy Zheng
1b36944299
anlogic: add latch cells
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Add latch cells to Anlogic cells replacement library by copying other
FPGAs' latch code to it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-25 22:47:46 +08:00
Icenowy Zheng
90d00182cf
anlogic: implement DRAM initialization
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As the TD tool doesn't accept the DRAM cell to contain unknown values in
the initial value, the initialzation support of DRAM is previously
skipped.
Now add the support by add a new pass to determine unknown values in the
initial value.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-20 07:56:15 +08:00
Clifford Wolf
93d44bb9a6
Merge pull request #752 from Icenowy/anlogic-lut-cost
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Anlogic: let LUT5/6 have more cost than LUT4-
2018-12-19 19:52:31 +01:00
Clifford Wolf
c98d44ac12
Merge pull request #753 from Icenowy/anlogic-makefile-fix
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anlogic: fix Makefile.inc
2018-12-19 19:51:10 +01:00
Icenowy Zheng
3993ba71f7
anlogic: fix Makefile.inc
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During the addition of DRAM inferring support, the installation of
eagle_bb.v is accidentally removed.
Fix this issue.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-19 10:23:58 +08:00
Icenowy Zheng
c9513c695a
Anlogic: let LUT5/6 have more cost than LUT4-
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According to the datasheet of Anlogic Eagle FPGAs, The LUTs natively
in an Anlogic FPGA is LUT4 (in MSLICEs) and "Enhanced LUT5" (in
LSLICEs). An "Enhanced LUT5" can be divided into two LUT4s.
So a LUT5 will cost around 2x resource of a LUT4, and a LUT6 will cost
2x resource of a LUT5.
Change the -lut parameter passed to the abc command to pass this cost
info to the ABC process.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-19 09:36:53 +08:00
Icenowy Zheng
4bf8ac728c
anlogic: set the init value of DFFs
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As dffinit has already supported for different initialization strings
for DFFs and check for re-initialization, initialization of Anlogic
DFFs are now ready to go.
Support for set the init values of Anlogic DFFs.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-18 23:16:37 +08:00
Icenowy Zheng
7854d5ba21
anlogic: fix dbits of Anlogic Eagle DRAM16X4
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The dbits of DRAM16X4 is wrong set to 2, which leads to waste of DRAM
bits.
Fix the dbits number in the RAM configuration.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-18 14:38:44 +08:00
Icenowy Zheng
d53a2bd1d3
anlogic: add support for Eagle Distributed RAM
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The MSLICEs on the Eagle series of FPGA can be configured as Distributed
RAM.
Enable to synthesis to DRAM.
As the Anlogic software suite doesn't support any 'bx to exist in the
initializtion data of DRAM, do not enable the initialization support of
the inferred DRAM.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-17 23:20:40 +08:00
Icenowy Zheng
634d7d1c14
Revert "Leave only real black box cells"
...
This reverts commit 43030db5ff
.
For a synthesis tool, generating EG_LOGIC cells are a good choice, as
they can be furtherly optimized when PnR, although sometimes EG_LOGIC is
not as blackbox as EG_PHY cells (because the latter is more close to the
hardware implementation).
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-17 23:20:40 +08:00
Clifford Wolf
5fa5dbbdda
Rename "fine:" label to "map:" in "synth_ice40"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-16 16:36:19 +01:00
Clifford Wolf
2a681909df
Merge pull request #724 from whitequark/equiv_opt
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equiv_opt: new command, for verifying optimization passes
2018-12-16 15:54:26 +01:00
Clifford Wolf
ceffa66dbd
Merge pull request #730 from smunaut/ffssr_dont_touch
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ice40: Honor the "dont_touch" attribute in FFSSR pass
2018-12-16 15:50:42 +01:00
Clifford Wolf
0c69f1d777
Merge pull request #725 from olofk/ram4k-init
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Only use non-blocking assignments of SB_RAM40_4K for yosys
2018-12-16 15:42:04 +01:00
Sylvain Munaut
add6ab9b2a
ice40: Honor the "dont_touch" attribute in FFSSR pass
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This is useful if you want to place FF manually ... can't merge SR in those
because it might make the manual placement invalid
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-12-08 22:46:28 +01:00
whitequark
7ff5a9db2d
equiv_opt: pass -D EQUIV when techmapping.
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This allows avoiding techmap crashes e.g. because of large memories
in white-box cell models.
2018-12-07 17:20:34 +00:00
Olof Kindgren
889297c62a
Only use non-blocking assignments of SB_RAM40_4K for yosys
...
In an initial statement, blocking assignments are normally used
and e.g. verilator throws a warning if non-blocking ones are used.
Yosys cannot however properly resolve the interdependencies if
blocking assignments are used in the initialization of SB_RAM_40_4K
and thus this has been used.
This patch will change to use non-blocking assignments only for yosys
2018-12-06 21:45:59 +01:00
whitequark
6e559ee3c7
synth_ice40: split `map_gates` off `fine`.
2018-12-06 12:04:39 +00:00
whitequark
d9fa4387c9
synth_ice40: add -noabc option, to use built-in LUT techmapping.
...
This should be combined with -relut to get sensible results.
2018-12-05 17:13:46 +00:00
whitequark
9ef078848a
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.
2018-12-05 17:13:27 +00:00
whitequark
12596b5003
Fix typo.
2018-12-05 17:13:27 +00:00
Clifford Wolf
e115303129
Merge pull request #713 from Diego-HR/master
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Changes in GoWin synth commands and ALU primitive support
2018-12-05 09:08:30 -08:00
Clifford Wolf
1a260ce89b
Merge pull request #712 from mmicko/anlogic-support
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Initial support for Anlogic FPGA
2018-12-05 09:08:04 -08:00
whitequark
45cb6200af
opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.
2018-12-05 16:30:37 +00:00
whitequark
ea4870b126
synth_ice40: add -relut option, to run ice40_unlut and opt_lut.
2018-12-05 16:30:37 +00:00
whitequark
1719aa88ac
Extract ice40_unlut pass from ice40_opt.
...
Currently, `ice40_opt -unlut` would map SB_LUT4 to $lut and convert
them back to logic immediately. This is not desirable if the goal
is to operate on $lut cells. If this is desirable, the same result
as `ice40_opt -unlut` can be achieved by running simplemap and opt
after ice40_unlut.
2018-12-05 16:30:24 +00:00
Diego H
819ca73096
Changes in GoWin synth commands and ALU primitive support
2018-12-03 20:08:35 -06:00
Miodrag Milanovic
43030db5ff
Leave only real black box cells
2018-12-02 11:57:50 +01:00
Miodrag Milanovic
83bce9f59c
Initial support for Anlogic FPGA
2018-12-01 18:28:54 +01:00
Sylvain Munaut
3e5ab50a73
ice40: Add option to only use CE if it'd be use by more than X FFs
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-27 21:50:42 +01:00
Clifford Wolf
dbc4cb8f4a
Merge pull request #697 from eddiehung/xilinx_ps7
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Add support for PS7 block for Xilinx
2018-11-12 09:09:22 +01:00
Clifford Wolf
317cc9c2b7
Merge pull request #695 from daveshah1/ecp5_bb
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ecp5: Adding some blackbox cells
2018-11-12 09:08:49 +01:00
Eddie Hung
99a14b0e37
Add support for Xilinx PS7 block
2018-11-10 12:45:07 -08:00
David Shah
fae3e645a2
ecp5: Add 'fake' DCU parameters
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-09 18:25:42 +00:00
David Shah
960c8794fa
ecp5: Add blackboxes for ancillary DCU cells
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-09 15:18:30 +00:00
David Shah
1f51332808
ecp5: Adding some blackbox cells
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-07 14:56:38 +00:00
Clifford Wolf
d084fb4c3f
Fix sf2 LUT interface
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-31 15:36:53 +01:00
Clifford Wolf
cf79fd4376
Basic SmartFusion2 and IGLOO2 synthesis support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-31 15:28:57 +01:00
David Shah
b65932edc4
ecp5: Remove DSP parameters that don't work
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-10-22 16:20:38 +01:00
David Shah
101f5234ff
ecp5: Add DSP blackboxes
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-10-21 19:27:02 +01:00
David Shah
d29b517fef
ecp5: Sim model fixes
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-19 15:16:40 +01:00
David Shah
677b8ed3ca
ecp5: Add latch inference
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-19 15:16:40 +01:00
Clifford Wolf
24a5c65856
Merge pull request #657 from mithro/xilinx-vpr
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xilinx: Still map LUT7/LUT8 to Xilinx specific primitives when using `-vpr`
2018-10-18 10:54:03 +02:00
David Shah
df4bfa0ad6
ecp5: Disable LSR inversion
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-16 12:48:39 +01:00
David Shah
812538a036
BRAM improvements
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-12 14:22:21 +01:00
David Shah
bdfead8c64
ecp5: Adding BRAM maps for all size options
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-10 17:18:17 +01:00
David Shah
983fb7ff88
ecp5: First BRAM type maps successfully
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-10 16:35:19 +01:00
David Shah
2ef1af8b58
ecp5: Script for BRAM IO connections
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-10 16:11:00 +01:00
David Shah
346cbbdbdc
ecp5: Adding BRAM initialisation and config
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-09 14:19:04 +01:00
Tim 'mithro' Ansell
b111ea1228
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.
...
Then if targeting vpr map all the Xilinx specific LUTs back into generic
Yosys LUTs.
2018-10-08 16:52:12 -07:00
David Shah
31e22c8b96
ecp5: Add blackbox for DP16KD
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-05 11:35:59 +01:00
Clifford Wolf
5f1fea08d5
Add inout ports to cells_xtra.v
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-04 11:30:55 +02:00
Tim Ansell
ad975fb694
xilinx: Adding missing inout IO port to IOBUF
2018-10-03 16:38:32 -07:00
Clifford Wolf
76baae4b94
Merge pull request #645 from daveshah1/ecp5_dram_fix
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ecp5: Don't map ROMs to DRAM
2018-10-02 10:00:10 +02:00
David Shah
fcd39e1398
ecp5: Don't map ROMs to DRAM
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-10-01 18:34:41 +01:00
Clifford Wolf
51f1bbeeb0
Add iCE40 SB_SPRAM256KA simulation model
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-10 11:57:24 +02:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
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o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
David Shah
3a3558acce
ecp5: Fixing miscellaneous sim model issues
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-16 15:56:12 +02:00
David Shah
e9ef077266
ecp5: Fixing 'X' issues with LUT simulation models
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-16 15:20:34 +02:00
David Shah
b2c62ff8ef
ecp5: ECP5 synthesis fixes
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-16 14:33:13 +02:00
David Shah
459d367913
ecp5: Adding synchronous set/reset support
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-14 16:18:01 +02:00
David Shah
241429abac
ecp5: Add DRAM match rule
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 16:25:52 +02:00
David Shah
4a60bc83ab
ecp5: Cells and mappings fixes
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 16:14:08 +02:00
David Shah
b0fea67cc6
ecp5: Fixing arith_map
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 15:49:59 +02:00
David Shah
11c916840d
ecp5: Initial arith_map implementation
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 15:46:12 +02:00
David Shah
c2d7be140a
ecp5: Adding basic synth_ecp5 based on synth_ice40
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 14:52:25 +02:00
David Shah
eb8f3f7dc4
ecp5: Adding DFF maps
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 14:32:23 +02:00
David Shah
1def34f2a6
ecp5: Adding DRAM map
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 14:08:42 +02:00
David Shah
b1b9e23f94
ecp5: Adding basic cells_sim and mapper for LUTs up to LUT7
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 13:27:24 +02:00
David Shah
cd65eeb3b3
ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 13:09:18 +02:00
Clifford Wolf
57fc8dd582
Add "synth_ice40 -json"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-13 13:35:10 +02:00
Clifford Wolf
83631555dd
Fix ice40_opt for cases where a port is connected to a signal with width != 1
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-11 18:12:42 +02:00
Clifford Wolf
7fecc3c199
Make -nordff the default in "prep"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-30 13:17:09 +02:00
Olof Kindgren
faac2c5595
Avoid mixing module port declaration styles in ice40 cells_sim.v
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The current code requires workarounds for several simulators
For modelsim, the file must be compiled with -mixedansiports and
xsim needs --relax.
2018-05-17 13:54:43 +02:00
Clifford Wolf
47eb150eec
Merge pull request #537 from mithro/yosys-vpr
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Improving Yosys when used with VPR
2018-05-04 12:32:30 +02:00
Clifford Wolf
b4c1d3084f
Add "synth_intel --noiopads"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-30 13:02:56 +02:00
Tim 'mithro' Ansell
d6bdefd2e9
Improving vpr output support.
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* Support output BLIF for Xilinx architectures.
* Support using .names in BLIF for Xilinx architectures.
* Use the same `NO_LUT` define in both `synth_ice40` and
`synth_xilinx`.
2018-04-18 16:55:12 -07:00
Tim 'mithro' Ansell
ca39e493ba
synth_ice40: Rework the vpr blif output slightly.
2018-04-18 16:55:08 -07:00
Clifford Wolf
81a457c4a6
Add "synth_ice40 -nodffe"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-16 20:44:26 +02:00
c60k28
efed2420d6
Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device
2018-03-31 22:48:47 -06:00
Robert Ou
14e49fb057
coolrunner2: Add an ANDTERM/XOR between chained FFs
...
In some cases (e.g. the low bits of counters) the design might end up
with a flip-flop whose input is directly driven by another flip-flop.
This isn't possible in the Coolrunner-II architecture, so add a single
AND term and XOR in this case.
2018-03-31 03:54:48 -07:00
Robert Ou
cfa3753b89
coolrunner2: Split multi-bit nets
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The PAR tool doesn't expect any "dangling" nets with no drivers nor
sinks. By splitting the nets, clean removes them.
2018-03-31 02:56:11 -07:00
Robert Ou
8fe9cdf364
coolrunner2: Add extraction for TFFs
2018-03-31 02:54:26 -07:00
Larry Doolittle
efaef82f75
Squelch trailing whitespace, including meta-whitespace
2018-03-11 16:03:41 +01:00
Clifford Wolf
6991c132b5
Add Xilinx RAM64X1D and RAM128X1D simulation models
2018-03-07 17:31:48 +01:00
Clifford Wolf
27dd500d31
Add "synth -noshare"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-04 17:13:45 +01:00
Clifford Wolf
eb67a7532b
Add $allconst and $allseq cell types
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-23 13:14:47 +01:00
Robert Ou
2abcd98527
coolrunner2: Move LOC attributes onto the IO cells
2018-01-17 16:17:32 -08:00
Clifford Wolf
9ac560f5d3
Add "dffinit -highlow" and fix synth_intel
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-09 18:42:19 +01:00
Clifford Wolf
b66d50e62d
Fix minor typo in "prep" help message
2017-12-19 21:44:05 +01:00
Graham Edgecombe
f93e6637aa
Fix port names in SB_IO_OD
2017-12-10 15:33:38 +00:00
Graham Edgecombe
52ace35a73
Remove trailing comma from SB_IO_OD port list
...
This isn't compatible with Icarus Verilog.
2017-12-10 15:33:38 +00:00
Tim Ansell
3cc31f197c
Fix spelling in -vpr help for synth_ice40
2017-12-08 18:44:45 -08:00
Clifford Wolf
1f6e8f86c5
Merge pull request #462 from daveshah1/up5k
...
Add remaining UltraPlus cells to ice40 techlib
2017-11-28 15:53:53 +01:00
David Shah
5e8d1922a4
Add remaining UltraPlus cells to ice40 techlib
2017-11-28 11:07:49 +00:00
Clifford Wolf
4782d59a3f
Merge pull request #455 from daveshah1/up5k
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Add UltraPlus specific cells to ice40 techlib
2017-11-18 19:12:48 +01:00
David Shah
0505f1043c
Remove unnecessary keep attributes
2017-11-18 17:53:21 +00:00
Clifford Wolf
c01df04e32
Merge pull request #453 from dh73/master
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Updating Intel FPGA subsystem with Cyclone 10, minor changes in examples/intel directory and Speedster cells
2017-11-18 09:56:36 +01:00
David Shah
8ae73e60e2
Merge branch 'master' into up5k
2017-11-17 15:15:39 +00:00
Clifford Wolf
234726c655
Add "synth_ice40 -vpr"
2017-11-16 21:37:02 +01:00
David Shah
f9f3ca5da0
Add some UltraPlus cells to ice40 techlib
2017-11-16 12:24:35 +00:00
dh73
3fd1d61e2a
Initial Cyclone 10 support
2017-11-08 22:45:21 -06:00
dh73
1fc061d90c
Organizing Speedster file names
2017-11-08 20:23:55 -06:00
Larry Doolittle
50bcd9a728
Clean whitespace and permissions in techlibs/intel
2017-10-05 16:23:49 +02:00
Clifford Wolf
65f91e5120
Rename "write_verilog -nobasenradix" to "write_verilog -decimal"
2017-10-03 17:31:21 +02:00
dh73
4718e65763
Tested and working altsyncarm without init files
2017-10-01 19:59:45 -05:00
dh73
cbaba62401
Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now
2017-10-01 11:04:17 -05:00
Clifford Wolf
c5b204d8d2
Add first draft of eASIC back-end
2017-09-29 17:53:43 +02:00
Clifford Wolf
e64b9d5a4d
Fix synth_ice40 doc regarding -top default
2017-09-29 17:52:57 +02:00
Andrew Zonenberg
122532b7e1
Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted.
2017-09-14 10:26:32 -07:00
Andrew Zonenberg
a84172b23b
Initial support for extraction of counters with clock enable
2017-09-14 10:26:10 -07:00
Clifford Wolf
2f75240e36
Merge pull request #406 from azonenberg/coolrunner-techmap
...
Coolrunner techmapping improvements
2017-09-02 13:43:51 +02:00
Robert Ou
5f65e24ccb
coolrunner2: Finish fixing special-use p-terms
2017-09-01 07:22:16 -07:00
Robert Ou
fa04366f38
coolrunner2: Generate a feed-through AND term when necessary
2017-09-01 07:22:01 -07:00
Robert Ou
6775177171
coolrunner2: Initial fixes for special p-terms
...
Certain signals can only be controlled by a product term and not a
sum-of-products. Do the initial work for fixing this.
2017-09-01 07:21:51 -07:00
Robert Ou
7f08be4304
coolrunner2: Fix mapping of flip-flops
2017-09-01 07:21:39 -07:00
Robert Ou
ac84f47829
coolrunner2: Combine some for loops together
2017-09-01 07:21:31 -07:00
Andrew Zonenberg
40021d2fd8
Fixed typo in error message
2017-09-01 06:45:10 -07:00
Andrew Zonenberg
fc0c7f74dc
Added blackbox $__COUNT_ cell model
2017-09-01 06:44:28 -07:00
Andrew Zonenberg
80aaf50302
Refactoring: moved modules still in cells_sim to cells_sim_wip
2017-09-01 06:44:15 -07:00
Andrew Zonenberg
06754108fc
Merge branch 'master' of https://github.com/cliffordwolf/yosys into counter-extraction
2017-08-30 16:40:41 -07:00
Andrew Zonenberg
634f18be96
extract_counter: Minor changes requested to comply with upstream policy, fixed a few typos
2017-08-30 16:28:25 -07:00
Andrew Zonenberg
3fc1b9f3fd
Finished refactoring counter extraction to be nice and generic. Implemented techmapping from $__COUNT_ to GP_COUNTx cells.
2017-08-28 22:18:57 -07:00
Andrew Zonenberg
b5c15636c5
Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to techmap/ since it's going to become a generic pass
2017-08-28 22:18:34 -07:00
Andrew Zonenberg
c3145863e7
Reformatted GP_COUNTx_ADV resets to avoid Yosys thinking that they're multi-edge-sensitive and getting confused.
2017-08-28 14:25:46 -07:00
Andrew Zonenberg
e62362225c
Fixed bug causing GP_SPI model to not synthesize
2017-08-27 07:31:48 -07:00
Andrew Zonenberg
e6eaf487b6
Fixed more issues with GreenPAK counter sim models
2017-08-15 09:18:36 -07:00
Andrew Zonenberg
3a404be62a
Updated PGEN model to have level triggered reset (matches actual hardware behavior
2017-08-15 09:18:27 -07:00
Andrew Zonenberg
e5109847c9
Fixed bug in GP_COUNTx model
2017-08-15 09:18:17 -07:00
Andrew Zonenberg
66b256d40e
Fixed bug where GP_COUNTx_ADV would wrap even when KEEP was high
2017-08-15 09:18:07 -07:00
Clifford Wolf
2cf0b5c157
Merge pull request #381 from azonenberg/countfix
...
Added better behavioral models for GreenPAK counters. Refactored cells_sim into two files so analog/mixed signal stuff is separate
2017-08-14 21:47:26 +02:00
Robert Ou
78fd24f40f
coolrunner2: Add INVERT parameter to some BUFGs
2017-08-14 12:13:33 -07:00
Robert Ou
1e3ffd57cb
coolrunner2: Add FFs with clock enable to cells_sim.v
2017-08-14 12:13:25 -07:00
Andrew Zonenberg
348acbd968
Fixed typo in GP_COUNT8 sim model
2017-08-14 10:45:40 -07:00
Andrew Zonenberg
c205d571df
Fixed typo in error message
2017-08-14 10:45:40 -07:00
Andrew Zonenberg
0a6c702c41
Changed LEVEL resets for GP_COUNTx to be properly synthesizeable
2017-08-14 10:45:40 -07:00