riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Make doc consistent

This commit is contained in:
Eddie Hung 2019-06-14 10:32:46 -07:00
parent 1656c44373
commit 627a62a797
3 changed files with 6 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
techlibs/common/synth.cc
View File

@ -76,7 +76,7 @@ struct SynthPass : public ScriptPass
log(" synonymous to the end of the command list.\n");
log("\n");
log(" -abc9\n");
log(" use abc9 instead of abc\n");
log(" use new ABC9 flow (EXPERIMENTAL)\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@ -174,6 +174,9 @@ struct SynthPass : public ScriptPass
if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n");
if (abc == "abc9" && !lut)
log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)");
log_header(design, "Executing SYNTH pass.\n");
log_push();

2
techlibs/ice40/synth_ice40.cc
View File

@ -97,7 +97,7 @@ struct SynthIce40Pass : public ScriptPass
log(" (this feature is experimental and incomplete)\n");
log("\n");
log(" -abc9\n");
log(" use abc9 instead of abc\n");
log(" use new ABC9 flow (EXPERIMENTAL)\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");

2
techlibs/xilinx/synth_xilinx.cc
View File

@ -82,7 +82,7 @@ struct SynthXilinxPass : public ScriptPass
log(" run 'abc' with -dff option\n");
log("\n");
log(" -abc9\n");
log(" use abc9 instead of abc\n");
log(" use new ABC9 flow (EXPERIMENTAL)\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");