riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fixed typo in GP_COUNT8 sim model

This commit is contained in:
Andrew Zonenberg 2017-08-11 16:55:31 -07:00
parent c205d571df
commit 348acbd968
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
techlibs/greenpak4/cells_sim_digital.v
View File

@ -411,7 +411,7 @@ module GP_COUNT8(
//Combinatorially output underflow flag whenever we wrap low
always @(*) begin
OUT <= (count == 8'h0);
OUT <= count;
POUT <= count;
end
//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.