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Fix SB_DFF comb model

This commit is contained in:
Eddie Hung 2019-04-18 23:07:16 -07:00
parent 0919f36b88
commit 19b660ff6e
2 changed files with 3 additions and 3 deletions
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2
techlibs/ice40/cells_sim.v
View File

@ -143,7 +143,7 @@ module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) in
always @(posedge C)
Q <= D;
`else
assign Q = D;
always @* Q = D;
`endif
endmodule

4
techlibs/ice40/synth_ice40.cc
View File

@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
{
if (check_label("begin"))
{
run("read_verilog -wb +/ice40/cells_sim.v");
run("read_verilog -wb -D ABC_FLOPS +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run("proc");
}
@ -293,7 +293,7 @@ struct SynthIce40Pass : public ScriptPass
run("techmap");
else
run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
if (retime || help_mode)
if ((retime || help_mode) && abc != "abc9")
run(abc + " -dff", "(only if -retime)");
run("ice40_opt");
}