mirror of https://github.com/YosysHQ/yosys.git
Clean up trimming leading 1'bx in A during techmappnig
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@ -170,19 +170,14 @@ module \$__XILINX_SHIFTX (A, B, Y);
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parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
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parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
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function integer compute_num_leading_X_in_A;
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integer i, c;
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function integer A_WIDTH_trimmed;
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input integer start;
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begin
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compute_num_leading_X_in_A = 0;
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c = 1;
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for (i = A_WIDTH-1; i >= 0; i=i-1) begin
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if (!_TECHMAP_CONSTMSK_A_[i] || _TECHMAP_CONSTVAL_A_[i] !== 1'bx)
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c = 0;
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compute_num_leading_X_in_A = compute_num_leading_X_in_A + c;
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end
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A_WIDTH_trimmed = start;
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while (A_WIDTH_trimmed > 0 && _TECHMAP_CONSTMSK_A_[A_WIDTH_trimmed-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH_trimmed-1] === 1'bx)
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A_WIDTH_trimmed = A_WIDTH_trimmed - 1;
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end
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endfunction
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localparam num_leading_X_in_A = compute_num_leading_X_in_A();
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generate
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genvar i, j;
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@ -200,11 +195,10 @@ module \$__XILINX_SHIFTX (A, B, Y);
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assign A_i[i] = A[i*2];
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\$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
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end
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// Trim off any leading 1'bx -es in A, and resize B accordingly
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else if (num_leading_X_in_A > 0) begin
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localparam A_WIDTH_new = A_WIDTH - num_leading_X_in_A;
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localparam B_WIDTH_new = $clog2(A_WIDTH_new);
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\$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH_new), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B[B_WIDTH_new-1:0]), .Y(Y));
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// Trim off any leading 1'bx -es in A
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else if (_TECHMAP_CONSTMSK_A_[A_WIDTH-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH-1] === 1'bx) begin
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localparam A_WIDTH_new = A_WIDTH_trimmed(A_WIDTH-1);
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\$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B), .Y(Y));
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end
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else if (A_WIDTH < `MIN_MUX_INPUTS) begin
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wire _TECHMAP_FAIL_ = 1;
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