mirror of https://github.com/YosysHQ/yosys.git
Fix ice40_opt for cases where a port is connected to a signal with width != 1
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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270c1814b5
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83631555dd
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@ -26,6 +26,13 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static SigBit get_bit_or_zero(const SigSpec &sig)
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{
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if (GetSize(sig) == 0)
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return State::S0;
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return sig[0];
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}
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static void run_ice40_opts(Module *module, bool unlut_mode)
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{
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pool<SigBit> optimized_co;
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@ -45,7 +52,11 @@ static void run_ice40_opts(Module *module, bool unlut_mode)
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SigSpec non_const_inputs, replacement_output;
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int count_zeros = 0, count_ones = 0;
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SigBit inbit[3] = {cell->getPort("\\I0"), cell->getPort("\\I1"), cell->getPort("\\CI")};
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SigBit inbit[3] = {
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get_bit_or_zero(cell->getPort("\\I0")),
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get_bit_or_zero(cell->getPort("\\I1")),
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get_bit_or_zero(cell->getPort("\\CI"))
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};
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for (int i = 0; i < 3; i++)
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if (inbit[i].wire == nullptr) {
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if (inbit[i] == State::S1)
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@ -63,8 +74,8 @@ static void run_ice40_opts(Module *module, bool unlut_mode)
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replacement_output = non_const_inputs;
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if (GetSize(replacement_output)) {
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optimized_co.insert(sigmap(cell->getPort("\\CO")));
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module->connect(cell->getPort("\\CO"), replacement_output);
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optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
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module->connect(cell->getPort("\\CO")[0], replacement_output);
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module->design->scratchpad_set_bool("opt.did_something", true);
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log("Optimized away SB_CARRY cell %s.%s: CO=%s\n",
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log_id(module), log_id(cell), log_signal(replacement_output));
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@ -78,10 +89,10 @@ static void run_ice40_opts(Module *module, bool unlut_mode)
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{
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SigSpec inbits;
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inbits.append(cell->getPort("\\I0"));
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inbits.append(cell->getPort("\\I1"));
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inbits.append(cell->getPort("\\I2"));
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inbits.append(cell->getPort("\\I3"));
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inbits.append(get_bit_or_zero(cell->getPort("\\I0")));
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inbits.append(get_bit_or_zero(cell->getPort("\\I1")));
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inbits.append(get_bit_or_zero(cell->getPort("\\I2")));
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inbits.append(get_bit_or_zero(cell->getPort("\\I3")));
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sigmap.apply(inbits);
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if (unlut_mode)
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@ -104,8 +115,13 @@ static void run_ice40_opts(Module *module, bool unlut_mode)
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cell->setParam("\\LUT", cell->getParam("\\LUT_INIT"));
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cell->unsetParam("\\LUT_INIT");
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cell->setPort("\\A", SigSpec({cell->getPort("\\I3"), cell->getPort("\\I2"), cell->getPort("\\I1"), cell->getPort("\\I0")}));
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cell->setPort("\\Y", cell->getPort("\\O"));
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cell->setPort("\\A", SigSpec({
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get_bit_or_zero(cell->getPort("\\I3")),
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get_bit_or_zero(cell->getPort("\\I2")),
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get_bit_or_zero(cell->getPort("\\I1")),
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get_bit_or_zero(cell->getPort("\\I0"))
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}));
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cell->setPort("\\Y", cell->getPort("\\O")[0]);
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cell->unsetPort("\\I0");
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cell->unsetPort("\\I1");
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cell->unsetPort("\\I2");
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