mirror of https://github.com/YosysHQ/yosys.git
Move techamp t:$_DFF_?N? to before abc call
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@ -111,10 +111,10 @@ struct SynthXilinxPass : public Pass
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log(" dff2dffe\n");
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log(" opt -full\n");
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log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n");
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log(" techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n");
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log(" opt -fast\n");
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log("\n");
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log(" map_luts:\n");
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log(" techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n");
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log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n");
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log(" clean\n");
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log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
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@ -261,7 +261,6 @@ struct SynthXilinxPass : public Pass
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} else {
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Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
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}
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Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?");
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Pass::call(design, "hierarchy -check");
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Pass::call(design, "opt -fast");
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@ -269,6 +268,7 @@ struct SynthXilinxPass : public Pass
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if (check_label(active, run_from, run_to, "map_luts"))
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{
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Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?");
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Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
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Pass::call(design, "clean");
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Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
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