mirror of https://github.com/YosysHQ/yosys.git
Merge branch 'map_cells_before_map_luts' into xc7srl
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commit
7b7ddbdba7
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@ -128,6 +128,7 @@ struct SynthXilinxPass : public Pass
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log(" abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)\n");
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log(" abc -lut 5 [-dff] (with '-vpr' only!)\n");
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log(" clean\n");
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log(" techmap -map +/xilinx/lut_map.v\n");
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log("\n");
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log(" check:\n");
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log(" hierarchy -check\n");
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